[coreboot-gerrit] Patch merged into coreboot/master: 1a8e0af tegra124: Setup clock PLLD by approximating display panel pixel clock.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 1a8e0af78b1886acc96d1e80be5871d287d148c5
Author: Hung-Te Lin <hungte at chromium.org>
Date:   Tue Apr 8 20:03:40 2014 +0800

    tegra124: Setup clock PLLD by approximating display panel pixel clock.
    
    PLLD, the clock for display, was previously hard-coded to 306MHz. To support
    more different panels, we should calcualte PLLD by panel pixel clock
    configuration.
    
    Note existing pixel clock configurations for nyan* boards won't work (they used
    to rely on hard-coded approximated values) so the device trees are also
    modified.
    
    BRANCH=none
    BUG=chrome-os-partner:25933
    TEST=emerge-nyan_big coreboot chromeos-bootimage
         See panel correctly initialized and got DEV screen.
    
    Original-Change-Id: I8d592f0cc044e7c4e4803c45955642e791210ad3
    Original-Signed-off-by: Hung-Te Lin <hungte at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/193565
    (cherry picked from commit 4f9b793633ebb2d104b0544e3b72fa0d105951c4)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Ib2cabbad60af010e872505e888eab485ba8c2916
    Reviewed-on: http://review.coreboot.org/7762
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/7762 for details.

-gerrit