[coreboot-gerrit] New patch to review for coreboot: 626cb0b intel/baytrail: Spelling fixes
Martin Roth (gaumless@gmail.com)
gerrit at coreboot.org
Sun Dec 7 23:01:33 CET 2014
Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7705
-gerrit
commit 626cb0b3b3e98c1fd9d254386fa18588ab1f1215
Author: Martin Roth <martin.roth at se-eng.com>
Date: Sun Dec 7 14:57:26 2014 -0700
intel/baytrail: Spelling fixes
Change-Id: Ideb58634a029d55746421ad1ea4b80811bca403c
Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
src/soc/intel/baytrail/baytrail/iosf.h | 4 ++--
src/soc/intel/baytrail/baytrail/irq.h | 2 +-
src/soc/intel/baytrail/baytrail/mrc_wrapper.h | 2 +-
src/soc/intel/baytrail/baytrail/smm.h | 2 +-
src/soc/intel/baytrail/northcluster.c | 2 +-
src/soc/intel/baytrail/pcie.c | 2 +-
src/soc/intel/baytrail/smihandler.c | 2 +-
src/soc/intel/baytrail/southcluster.c | 4 ++--
src/soc/intel/baytrail/spi.c | 4 ++--
src/soc/intel/baytrail/tsc_freq.c | 4 ++--
10 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h
index 9da86f5..220d022 100644
--- a/src/soc/intel/baytrail/baytrail/iosf.h
+++ b/src/soc/intel/baytrail/baytrail/iosf.h
@@ -63,7 +63,7 @@ uint32_t iosf_bunit_read(int reg);
void iosf_bunit_write(int reg, uint32_t val);
uint32_t iosf_dunit_read(int reg);
void iosf_dunit_write(int reg, uint32_t val);
-/* Some registers are per channel while the gloals live in dunit 0 */
+/* Some registers are per channel while the globals live in dunit 0 */
uint32_t iosf_dunit_ch0_read(int reg);
uint32_t iosf_dunit_ch1_read(int reg);
uint32_t iosf_punit_read(int reg);
@@ -106,7 +106,7 @@ void iosf_ssus_write(int reg, uint32_t val);
#define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */
#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */
#define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */
-#define IOSF_PORT_BUNIT 0x03 /* System Memroy Arbiter/Bunit */
+#define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */
#define IOSF_PORT_PMC 0x04 /* Power Management Controller */
#define IOSF_PORT_GFX 0x06 /* Graphics Adapter */
#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */
diff --git a/src/soc/intel/baytrail/baytrail/irq.h b/src/soc/intel/baytrail/baytrail/irq.h
index e66fab5..34b3f7d 100644
--- a/src/soc/intel/baytrail/baytrail/irq.h
+++ b/src/soc/intel/baytrail/baytrail/irq.h
@@ -127,7 +127,7 @@
# define SCIS_IRQ22 0x06
# define SCIS_IRQ23 0x07
-/* In each mainbaord directory there should exist a header file irqroute.h that
+/* In each mainboard directory there should exist a header file irqroute.h that
* defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which
* consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */
diff --git a/src/soc/intel/baytrail/baytrail/mrc_wrapper.h b/src/soc/intel/baytrail/baytrail/mrc_wrapper.h
index b5009e4..355dce0 100644
--- a/src/soc/intel/baytrail/baytrail/mrc_wrapper.h
+++ b/src/soc/intel/baytrail/baytrail/mrc_wrapper.h
@@ -65,7 +65,7 @@ struct mrc_mainboard_params {
int dram_is_slotted; /* mobo has DRAM slots. */
/*
* The below ODT settings are only honored when !dram_is_slotted.
- * Aditionally, weaker_odt_settings being non-zero causes
+ * Additionally, weaker_odt_settings being non-zero causes
* cpu_odt_value to not be honored as weaker_odt_settings have a
* special training path.
*/
diff --git a/src/soc/intel/baytrail/baytrail/smm.h b/src/soc/intel/baytrail/baytrail/smm.h
index f147f73..5ead89f 100644
--- a/src/soc/intel/baytrail/baytrail/smm.h
+++ b/src/soc/intel/baytrail/baytrail/smm.h
@@ -22,7 +22,7 @@
/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig
* is included after chipset code. This causes the chipset's Kconfig to be
- * cloberred by the arch/x86/Kconfig if they have the same name. */
+ * clobbered by the arch/x86/Kconfig if they have the same name. */
static inline int smm_region_size(void)
{
/* Make it 8MiB by default. */
diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c
index b119e24..8ff9712 100644
--- a/src/soc/intel/baytrail/northcluster.c
+++ b/src/soc/intel/baytrail/northcluster.c
@@ -50,7 +50,7 @@
* +--------------------------+ 0
*
* Note that there are really only a few regions that need to enumerated w.r.t.
- * coreboot's resrouce model:
+ * coreboot's resource model:
*
* +--------------------------+ BMBOUND_HI
* | Cacheable/Usable |
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index 4498f43..71b90de 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -80,7 +80,7 @@ static const struct reg_script init_static_after_exit_latency[] = {
REG_PCI_RMW16(DSTS2, ~CTD, 0x6),
/* Enable AER */
REG_PCI_OR16(DCTL_DSTS, URE | FEE | NFE | CEE),
- /* Read and write back capabaility registers. */
+ /* Read and write back capability registers. */
REG_PCI_OR32(0x34, 0),
REG_PCI_OR32(0x80, 0),
/* Retrain the link. */
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 62de9fa..a2718e2 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -392,7 +392,7 @@ void southbridge_smi_handler(void)
southbridge_smi[i]();
} else {
printk(BIOS_DEBUG,
- "SMI_STS[%d] occured, but no "
+ "SMI_STS[%d] occurred, but no "
"handler available.\n", i);
}
}
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 500a13d..5274b03 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -158,7 +158,7 @@ static void com1_configure_resume(device_t dev)
{
const uint16_t port = 0x3f8;
- /* Is the UART I/O port eanbled? */
+ /* Is the UART I/O port enabled? */
if (!(pci_read_config32(dev, UART_CONT) & 1))
return;
@@ -223,7 +223,7 @@ static void sc_init(device_t dev)
* Common code for the south cluster devices.
*/
-/* Set bit in function disble register to hide this device. */
+/* Set bit in function disable register to hide this device. */
static void sc_disable_devfn(device_t dev)
{
const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index 8677b61..10dbe44 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -565,7 +565,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
/*
* This is a 'no data' command (like Write Enable), its
- * bitesout size was 1, decremented to zero while executing
+ * bytesout size was 1, decremented to zero while executing
* spi_setup_opcode() above. Tell the chip to send the
* command.
*/
@@ -585,7 +585,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
}
/*
- * Check if this is a write command atempting to transfer more bytes
+ * Check if this is a write command attempting to transfer more bytes
* than the controller can handle. Iterations for writes are not
* supported here because each SPI write command needs to be preceded
* and followed by other SPI commands, and this sequence is controlled
diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c
index 90f154c..da7e965 100644
--- a/src/soc/intel/baytrail/tsc_freq.c
+++ b/src/soc/intel/baytrail/tsc_freq.c
@@ -68,11 +68,11 @@ void set_max_freq(void)
msr.lo |= (1 << 16);
wrmsr(MSR_IA32_MISC_ENABLES, msr);
- /* Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
+ /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
* the PERF_CTL. */
msr = rdmsr(MSR_IACORE_RATIOS);
perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
- /* Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
+ /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
* the PERF_CTL. */
msr = rdmsr(MSR_IACORE_VIDS);
perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
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