[coreboot-gerrit] New patch to review for coreboot: e808a4c samsung/exynos5420: Spelling Fixes
Martin Roth (gaumless@gmail.com)
gerrit at coreboot.org
Sun Dec 7 23:01:30 CET 2014
Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7703
-gerrit
commit e808a4cad7c6abc5e0d6766eb83654a704e6da41
Author: Martin Roth <martin.roth at se-eng.com>
Date: Sun Dec 7 14:59:11 2014 -0700
samsung/exynos5420: Spelling Fixes
Change-Id: I966645c83ae78943a7dbb9dc05af4fded6f4e5b5
Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
src/soc/samsung/exynos5420/clk.h | 14 +++++++-------
src/soc/samsung/exynos5420/clock.c | 10 +++++-----
src/soc/samsung/exynos5420/cpu.c | 2 +-
src/soc/samsung/exynos5420/dmc.h | 2 +-
src/soc/samsung/exynos5420/dmc_common.c | 6 +++---
src/soc/samsung/exynos5420/dmc_init_ddr3.c | 6 +++---
src/soc/samsung/exynos5420/dp.c | 4 ++--
src/soc/samsung/exynos5420/dp_lowlevel.c | 10 +++++-----
src/soc/samsung/exynos5420/fimd.c | 2 +-
src/soc/samsung/exynos5420/fimd.h | 2 +-
src/soc/samsung/exynos5420/gpio.h | 2 +-
src/soc/samsung/exynos5420/setup.h | 4 ++--
src/soc/samsung/exynos5420/smp.c | 2 +-
src/soc/samsung/exynos5420/spi.c | 2 +-
src/soc/samsung/exynos5420/tmu.c | 4 ++--
src/soc/samsung/exynos5420/tmu.h | 2 +-
src/soc/samsung/exynos5420/uart.c | 4 ++--
17 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/src/soc/samsung/exynos5420/clk.h b/src/soc/samsung/exynos5420/clk.h
index 6b7f472..0b56f46 100644
--- a/src/soc/samsung/exynos5420/clk.h
+++ b/src/soc/samsung/exynos5420/clk.h
@@ -47,11 +47,11 @@ unsigned long get_uart_clk(int dev_index);
void set_mmc_clk(int dev_index, unsigned int div);
/**
- * get the clk frequency of the required peripherial
+ * get the clk frequency of the required peripheral
*
- * @param peripherial Peripherial id
+ * @param peripheral Peripheral id
*
- * @return frequency of the peripherial clk
+ * @return frequency of the peripheral clk
*/
unsigned long clock_get_periph_rate(enum periph_id peripheral);
@@ -61,7 +61,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral);
#define MCT_HZ 24000000
/*
- * Set mshci controller instances clock drivder
+ * Set mshci controller instances clock divider
*
* @param enum periph_id instance of the mshci controller
*
@@ -70,7 +70,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral);
int clock_set_mshci(enum periph_id peripheral);
/*
- * Set dwmci controller instances clock drivder
+ * Set dwmci controller instances clock divider
*
* @param enum periph_id instance of the dwmci controller
*
@@ -81,7 +81,7 @@ int clock_set_dwmci(enum periph_id peripheral);
/*
* Sets the epll clockrate
*
- * @param rate Required clock rate to the presacaler in Hz
+ * @param rate Required clock rate to the prescaler in Hz
*
* Return 0 if ok else -1
*/
@@ -664,7 +664,7 @@ static struct exynos5_mct * const exynos_mct =
(void *)EXYNOS5_MULTI_CORE_TIMER_BASE;
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
-#define EPLL_SRC_CLOCK 24000000 /*24 MHz Cristal Input */
+#define EPLL_SRC_CLOCK 24000000 /*24 MHz Crystal Input */
#define TIMEOUT_EPLL_LOCK 1000
#define AUDIO_0_RATIO_MASK 0x0f
diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c
index 7043310..5bbeb04 100644
--- a/src/soc/samsung/exynos5420/clock.c
+++ b/src/soc/samsung/exynos5420/clock.c
@@ -28,7 +28,7 @@
/* input clock of PLL: SMDK5420 has 24MHz input clock */
#define CONFIG_SYS_CLK_FREQ 24000000
-/* Epll Clock division values to achive different frequency output */
+/* Epll Clock division values to achieve different frequency output */
static struct st_epll_con_val epll_div[] = {
{ 192000000, 0, 48, 3, 1, 0 },
{ 180000000, 0, 45, 3, 1, 0 },
@@ -336,7 +336,7 @@ int clock_set_dwmci(enum periph_id peripheral)
return -1;
}
- /* The SDCLKIN is divided insided controller by the DIVRATIO field in
+ /* The SDCLKIN is divided inside the controller by the DIVRATIO field in
* CLKSEL register, so we must calculate clock value as
* cclk_in = SDCLKIN / (DIVRATIO + 1)
* Currently the RIVRATIO must be 3 for MMC0 and MMC2 on Exynos5420
@@ -360,7 +360,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
u32 *reg;
/*
- * For now we only handle a very small subset of peipherals here.
+ * For now we only handle a very small subset of peripherals here.
* Others will need to (and do) mangle the clock registers
* themselves, At some point it is hoped that this function can work
* from a table or calculated register offset / mask. For now this
@@ -585,7 +585,7 @@ int clock_epll_set_rate(unsigned long rate)
epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
/*
- * Required period ( in cycles) to genarate a stable clock output.
+ * Required period ( in cycles) to generate a stable clock output.
* The maximum clock time can be up to 3000 * PDIV cycles of PLLs
* frequency input (as per spec)
*/
@@ -622,7 +622,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
unsigned int div ;
if ((dst_frq == 0) || (src_frq == 0)) {
- printk(BIOS_DEBUG, "%s: Invalid requency input for prescaler\n", __func__);
+ printk(BIOS_DEBUG, "%s: Invalid frequency input for prescaler\n", __func__);
printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq);
return -1;
}
diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c
index c904636..e8649a0 100644
--- a/src/soc/samsung/exynos5420/cpu.c
+++ b/src/soc/samsung/exynos5420/cpu.c
@@ -111,7 +111,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase,
*
* Note: We may want to do something clever to ensure the framebuffer
* region is aligned such that we don't change dcache policy for other
- * stuff inadvertantly.
+ * stuff inadvertently.
*/
uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
diff --git a/src/soc/samsung/exynos5420/dmc.h b/src/soc/samsung/exynos5420/dmc.h
index d12e2db..7b3e8bf 100644
--- a/src/soc/samsung/exynos5420/dmc.h
+++ b/src/soc/samsung/exynos5420/dmc.h
@@ -399,7 +399,7 @@ struct mem_timings {
uint8_t chips_per_channel; /* number of chips per channel */
uint8_t chips_to_configure; /* number of chips to configure */
uint8_t send_zq_init; /* 1 to send this command */
- unsigned int impedance; /* drive strength impedeance */
+ unsigned int impedance; /* drive strength impedance */
uint8_t gate_leveling_enable; /* check gate leveling is enabled */
};
diff --git a/src/soc/samsung/exynos5420/dmc_common.c b/src/soc/samsung/exynos5420/dmc_common.c
index 433312e..e651b7f 100644
--- a/src/soc/samsung/exynos5420/dmc_common.c
+++ b/src/soc/samsung/exynos5420/dmc_common.c
@@ -63,7 +63,7 @@ int dmc_config_zq(struct mem_timings *mem,
val &= ~ZQ_MANUAL_STR;
/*
- * Since we are manaully calibrating the ZQ values,
+ * Since we are manually calibrating the ZQ values,
* we are looping for the ZQ_init to complete.
*/
i = ZQ_INIT_TIMEOUT;
@@ -96,12 +96,12 @@ void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode)
writel(val, &dmc->phycontrol0);
}
- /* Update DLL Information: Force DLL Resyncronization */
+ /* Update DLL Information: Force DLL Resynchronization */
val = readl(&dmc->phycontrol0);
val |= FP_RSYNC;
writel(val, &dmc->phycontrol0);
- /* Reset Force DLL Resyncronization */
+ /* Reset Force DLL Resynchronization */
val = readl(&dmc->phycontrol0);
val &= ~FP_RSYNC;
writel(val, &dmc->phycontrol0);
diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c
index 4acf7d1..28603ae 100644
--- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c
@@ -143,7 +143,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
writel(mem->membaseconfig1, &exynos_tzasc1->membaseconfig1);
}
- /* Memory Channel Inteleaving Size
+ /* Memory Channel Interleaving Size
* Exynos5420 Channel interleaving = 128 bytes
*/
/* MEMCONFIG0/1 */
@@ -158,7 +158,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
&exynos_drex1->prechconfig0);
- /* TimingRow, TimingData, TimingPower and Timingaref
+ /* TimingRow, TimingData, TimingPower and Timingref
* values as per Memory AC parameters
*/
writel(mem->timing_ref, &exynos_drex0->timingref);
@@ -184,7 +184,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
/*
* During Suspend-Resume & S/W-Reset, as soon as PMU releases
* pad retention, CKE goes high. This causes memory contents
- * not to be retained during DRAM initialization. Therfore,
+ * not to be retained during DRAM initialization. Therefore,
* there is a new control register(0x100431e8[28]) which lets us
* release pad retention and retain the memory content until the
* initialization is complete.
diff --git a/src/soc/samsung/exynos5420/dp.c b/src/soc/samsung/exynos5420/dp.c
index b147035..4c54b4f 100644
--- a/src/soc/samsung/exynos5420/dp.c
+++ b/src/soc/samsung/exynos5420/dp.c
@@ -218,7 +218,7 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
printk(BIOS_ERR, "DP Wrong MAX LINK RATE : %x\n", temp);
return -1;
}
- /*Refer VESA Display Port Stnadard Ver1.1a Page 120 */
+ /*Refer VESA Display Port Standard Ver1.1a Page 120 */
if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
@@ -420,7 +420,7 @@ static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
unsigned char buf;
unsigned int dpcd_addr;
- /*lane_num value is used as arry index, so this range 0 ~ 3 */
+ /*lane_num value is used as array index, so this range 0 ~ 3 */
dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c
index 2b2418e..e8892cd 100644
--- a/src/soc/samsung/exynos5420/dp_lowlevel.c
+++ b/src/soc/samsung/exynos5420/dp_lowlevel.c
@@ -105,7 +105,7 @@ static void exynos_dp_init_analog_param(void)
/*
* Set termination
- * Normal bandgap, Normal swing, Tx terminal registor 61 ohm
+ * Normal bandgap, Normal swing, Tx terminal resistor 61 ohm
* 24M Phy clock, TX digital logic power is 100:1.0625V
*/
reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
@@ -160,7 +160,7 @@ static void exynos_dp_init_interrupt(void)
*/
lwrite32(INT_POL, &dp_regs->int_ctl);
- /* Clear pending regisers */
+ /* Clear pending registers */
lwrite32(0xff, &dp_regs->common_int_sta1);
lwrite32(0xff, &dp_regs->common_int_sta2);
lwrite32(0xff, &dp_regs->common_int_sta3);
@@ -350,7 +350,7 @@ void exynos_dp_init_hpd(void)
{
u32 reg;
- /* Clear interrupts releated to Hot Plug Dectect */
+ /* Clear interrupts related to Hot Plug Detect */
reg = HOTPLUG_CHG | HPD_LOST | PLUG;
lwrite32(reg, &dp_regs->common_int_sta4);
@@ -380,7 +380,7 @@ void exynos_dp_init_aux(void)
{
u32 reg;
- /* Clear inerrupts related to AUX channel */
+ /* Clear interrupts related to AUX channel */
reg = RPLY_RECEIV | AUX_ERR;
lwrite32(reg, &dp_regs->int_sta);
@@ -804,7 +804,7 @@ int exynos_dp_read_bytes_from_i2c(u32 device_addr,
/*
* If Rx sends defer, Tx sends only reads
- * request without sending addres
+ * request without sending address
*/
if (!defer)
retval =
diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c
index 1e51712..6cb8eb2 100644
--- a/src/soc/samsung/exynos5420/fimd.c
+++ b/src/soc/samsung/exynos5420/fimd.c
@@ -93,7 +93,7 @@ static void exynos_fimd_set_dualrgb(vidinfo_t *vid, unsigned int enabled)
cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
EXYNOS_DUALRGB_VDEN_EN_ENABLE;
- /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
+ /* in case of Line Split mode, MAIN_CNT doesn't need to be set. */
cfg |= EXYNOS_DUALRGB_SUB_CNT(vid->vl_col / 2) |
EXYNOS_DUALRGB_MAIN_CNT(0);
}
diff --git a/src/soc/samsung/exynos5420/fimd.h b/src/soc/samsung/exynos5420/fimd.h
index 41e5ccd..fa1e27a 100644
--- a/src/soc/samsung/exynos5420/fimd.h
+++ b/src/soc/samsung/exynos5420/fimd.h
@@ -93,7 +93,7 @@ struct exynos5_fimd_panel {
unsigned int right_margin; /* Horizontal Frontporch */
unsigned int hsync; /* Horizontal Sync Pulse Width */
unsigned int xres; /* X Resolution */
- unsigned int yres; /* Y Resopultion */
+ unsigned int yres; /* Y Resolution */
};
/* LCDIF Register Map */
diff --git a/src/soc/samsung/exynos5420/gpio.h b/src/soc/samsung/exynos5420/gpio.h
index 4cf8e57..ea1cd2f 100644
--- a/src/soc/samsung/exynos5420/gpio.h
+++ b/src/soc/samsung/exynos5420/gpio.h
@@ -544,7 +544,7 @@ int gpio_set_value(unsigned gpio, int value);
enum mvl3 {
LOGIC_0,
LOGIC_1,
- LOGIC_Z, /* high impedence / tri-stated / floating */
+ LOGIC_Z, /* high impedance / tri-stated / floating */
};
#endif /* CPU_SAMSUNG_EXYNOS5420_GPIO_H */
diff --git a/src/soc/samsung/exynos5420/setup.h b/src/soc/samsung/exynos5420/setup.h
index 63e40a8..e0a7d1b 100644
--- a/src/soc/samsung/exynos5420/setup.h
+++ b/src/soc/samsung/exynos5420/setup.h
@@ -790,7 +790,7 @@ struct exynos5_phy_control;
#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
#define CTRL_ATGATE (1 << 6)
-#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
+#define FP_RSYNC (1 << 3) /* Force DLL resynchronization */
/* Driver strength for CK, CKE, CS & CA */
#define IMP_OUTPUT_DRV_40_OHM 0x5
@@ -809,7 +809,7 @@ struct exynos5_phy_control;
struct mem_timings;
-/* Errors that we can encourter in low-level setup */
+/* Errors that we can encounter in low-level setup */
enum {
SETUP_ERR_OK,
SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c
index 6fc2fb0..41a57ab 100644
--- a/src/soc/samsung/exynos5420/smp.c
+++ b/src/soc/samsung/exynos5420/smp.c
@@ -267,7 +267,7 @@ static void power_down_core(void)
wfi();
}
-/* Configures the CPU states shard memory page and then shutdown all cores. */
+/* Configures the CPU states shared memory page and then shutdown all cores. */
static void configure_secondary_cores(void)
{
if (get_bits(read_midr(), 4, 12) == PART_NUMBER_CORTEX_A15) {
diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c
index c6c08e9..a2bbbb3 100644
--- a/src/soc/samsung/exynos5420/spi.c
+++ b/src/soc/samsung/exynos5420/spi.c
@@ -168,7 +168,7 @@ static int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes,
if (espi->half_duplex) {
step = 1;
} else if ((rx_bytes | tx_bytes | (uintptr_t)rxp |(uintptr_t)txp) & 3) {
- printk(BIOS_CRIT, "%s: WARNING: tranfer mode decreased to 1B\n",
+ printk(BIOS_CRIT, "%s: WARNING: transfer mode decreased to 1B\n",
__func__);
step = 1;
} else {
diff --git a/src/soc/samsung/exynos5420/tmu.c b/src/soc/samsung/exynos5420/tmu.c
index 1b04b6c..ea706cb 100644
--- a/src/soc/samsung/exynos5420/tmu.c
+++ b/src/soc/samsung/exynos5420/tmu.c
@@ -69,8 +69,8 @@ struct tmu_info exynos5420_tmu_info = {
/*
* After reading temperature code from register, compensating
- * its value and calculating celsius temperatue,
- * get current temperatue.
+ * its value and calculating celsius temperature,
+ * get current temperature.
*
* @return current temperature of the chip as sensed by TMU
*/
diff --git a/src/soc/samsung/exynos5420/tmu.h b/src/soc/samsung/exynos5420/tmu.h
index 3085b07..f71c899 100644
--- a/src/soc/samsung/exynos5420/tmu.h
+++ b/src/soc/samsung/exynos5420/tmu.h
@@ -66,7 +66,7 @@ enum tmu_status_t {
TMU_STATUS_TRIPPED,
};
-/* Tmeperature threshold values for various thermal events */
+/* Temperature threshold values for various thermal events */
struct temperature_params {
/* minimum value in temperature code range */
unsigned int min_val;
diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c
index b7ef0cb..4d71155 100644
--- a/src/soc/samsung/exynos5420/uart.c
+++ b/src/soc/samsung/exynos5420/uart.c
@@ -36,7 +36,7 @@
* The coefficient, used to calculate the baudrate on S5P UARTs is
* calculated as
* C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
- * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
+ * however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1,
* 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
*/
static const int udivslot[] = {
@@ -120,7 +120,7 @@ static int exynos5_uart_err_check(struct s5p_uart *uart, int op)
/*
* Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
+ * otherwise. When the function is successful, the character read is
* written into its argument c.
*/
static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart)
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