[coreboot-gerrit] Patch set updated for coreboot: 9924a3c acer/aoa150: Manual fixups on top of autport.

[Vladimir Serbinenko (phcoder@gmail.com)]

Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7573

-gerrit

commit 9924a3cd20312df0e3a45344ca760fd574602b72
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Sat Nov 22 13:20:28 2014 +0100

    acer/aoa150: Manual fixups on top of autport.
    
    * Chip is 1M and not 2M.
    * First 64K are used by EC. Leave them alone.
    * Half of the RAM is soldered and has no EEPROM. Just use hardcoded SPD.
    
    Change-Id: I5d6c3ad5f45d88c346b8c2142fb115d1c3317e12
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
 src/mainboard/acer/aoa150/Kconfig             |   7 ++++++-
 src/mainboard/acer/aoa150/Makefile.inc        |   3 +++
 src/mainboard/acer/aoa150/early_southbridge.c |  15 +++++++++++----
 src/mainboard/acer/aoa150/spd.bin             | Bin 0 -> 128 bytes
 4 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/acer/aoa150/Kconfig b/src/mainboard/acer/aoa150/Kconfig
index 99a4bb3..afe5367 100644
--- a/src/mainboard/acer/aoa150/Kconfig
+++ b/src/mainboard/acer/aoa150/Kconfig
@@ -3,7 +3,7 @@ if BOARD_ACER_AOA150
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select BOARD_ROMSIZE_KB_2048
+	select BOARD_ROMSIZE_KB_1024
 	select CHANNEL_XOR_RANDOMIZATION
 	select CPU_INTEL_SOCKET_441
 	select EARLY_CBMEM_INIT
@@ -36,6 +36,11 @@ config VGA_BIOS_ID
 	string
 	default "8086,27ae"
 
+# First 64K are used by EC
+config CBFS_SIZE
+	hex
+	default 0xf0000
+
 config DCACHE_RAM_BASE
 	hex
 	default 0xffdf8000
diff --git a/src/mainboard/acer/aoa150/Makefile.inc b/src/mainboard/acer/aoa150/Makefile.inc
index 2f60428..f71df63 100644
--- a/src/mainboard/acer/aoa150/Makefile.inc
+++ b/src/mainboard/acer/aoa150/Makefile.inc
@@ -1,2 +1,5 @@
 romstage-y += early_southbridge.c
 ramstage-y += cstates.c
+cbfs-files-y += spd.bin
+spd.bin-file := spd.bin
+spd.bin-type := raw
diff --git a/src/mainboard/acer/aoa150/early_southbridge.c b/src/mainboard/acer/aoa150/early_southbridge.c
index 6eda5b8..a334212 100644
--- a/src/mainboard/acer/aoa150/early_southbridge.c
+++ b/src/mainboard/acer/aoa150/early_southbridge.c
@@ -1,4 +1,6 @@
 #include <stdint.h>
+#include <cbfs.h>
+#include <string.h>
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
@@ -6,13 +8,18 @@
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
 
-/* FIXME: hardcoded. */
 void mainboard_get_spd(spd_raw_data *spd)
 {
-	read_spd(&spd[0], 0x50);
+	void *spd_file;
+	size_t spd_file_len = 0;
+	/* C0S0 is a soldered RAM with no real SPD. Use stored SPD.  */
+	spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", CBFS_TYPE_RAW,
+					 &spd_file_len);
+	if (spd_file && spd_file_len >= 128)
+		memcpy(&spd[0], spd_file, 128);
+
+	/* C0S0 is a DIMM slot.  */
 	read_spd(&spd[1], 0x51);
-	read_spd(&spd[2], 0x52);
-	read_spd(&spd[3], 0x53);
 }
 
 void setup_ich7_gpios(void)
diff --git a/src/mainboard/acer/aoa150/spd.bin b/src/mainboard/acer/aoa150/spd.bin
new file mode 100644
index 0000000..aec1a53
Binary files /dev/null and b/src/mainboard/acer/aoa150/spd.bin differ