[coreboot-gerrit] New patch to review for coreboot: c1603c6 arm: Get rid of the INTERMEDIATE variable used on exynos.

[Isaac Christensen (isaac.christensen@se-eng.com)]

Isaac Christensen (isaac.christensen at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6714

-gerrit

commit c1603c670bb0abf92b922849ce766344b65e0baf
Author: Gabe Black <gabeblack at google.com>
Date:   Thu Sep 26 23:21:57 2013 -0700

    arm: Get rid of the INTERMEDIATE variable used on exynos.
    
    The INTERMEDIATE variable was used to hook dd-ing the BL1 into the image for
    Exynos SOCs, but we can do that directly without having a special hook.
    
    Change-Id: I434506b52ca4ea1d01e25a785cbfe66dfdea21c4
    Signed-off-by: Gabe Black <gabeblack at google.com>
    Reviewed-on: https://chromium-review.googlesource.com/170921
    Reviewed-by: Hung-Te Lin <hungte at chromium.org>
    Commit-Queue: Gabe Black <gabeblack at chromium.org>
    Tested-by: Gabe Black <gabeblack at chromium.org>
    (cherry picked from commit 8db03c387ad654227d064e2a7fa5ecf09d07e3c5)
    Signed-off-by: Isaac Christensen <isaac.christensen at se-eng.com>
---
 src/cpu/samsung/exynos5250/Makefile.inc | 10 +++++-----
 src/cpu/samsung/exynos5420/Makefile.inc | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc
index 4b967b0..762b940 100644
--- a/src/cpu/samsung/exynos5250/Makefile.inc
+++ b/src/cpu/samsung/exynos5250/Makefile.inc
@@ -1,8 +1,3 @@
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE += exynos5250_add_bl1
-
 bootblock-y += spi.c alternate_cbfs.c
 bootblock-y += pinmux.c mct.c power.c
 # Clock is required for UART
@@ -54,6 +49,11 @@ ramstage-y += fb.c
 ramstage-y += usb.c
 ramstage-y += cbmem.c
 
+# Run an intermediate step when producing coreboot.rom
+# that adds additional components to the final firmware
+# image outside of CBFS
+.PHONY: exynos5250_add_bl1
+$(obj)/coreboot.rom: exynos5250_add_bl1
 exynos5250_add_bl1: $(obj)/coreboot.pre
 	printf "    DD         Adding Samsung Exynos5250 BL1\n"
 	dd if=3rdparty/cpu/samsung/exynos5250/bl1.bin \
diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc
index 897944c..cbf9882 100644
--- a/src/cpu/samsung/exynos5420/Makefile.inc
+++ b/src/cpu/samsung/exynos5420/Makefile.inc
@@ -1,8 +1,3 @@
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE += exynos5420_add_bl1
-
 bootblock-y += spi.c alternate_cbfs.c
 bootblock-y += pinmux.c mct.c power.c
 # Clock is required for UART
@@ -54,6 +49,11 @@ ramstage-y += dp.c dp_lowlevel.c fimd.c
 ramstage-y += usb.c
 ramstage-y += cbmem.c
 
+# Run an intermediate step when producing coreboot.rom
+# that adds additional components to the final firmware
+# image outside of CBFS
+.PHONY: exynos5420_add_bl1
+$(obj)/coreboot.rom: exynos5420_add_bl1
 exynos5420_add_bl1: $(obj)/coreboot.pre
 	printf "    DD         Adding Samsung Exynos5420 BL1\n"
 	dd if=3rdparty/cpu/samsung/exynos5420/bl1.bin \