[coreboot-gerrit] Patch set updated for coreboot: 29b8d0f lenovo/x60/i915.c: Place GTT below top of memory

Paul Menzel (paulepanter@users.sourceforge.net) gerrit at coreboot.org
Fri Aug 15 11:34:03 CEST 2014


Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927

-gerrit

commit 29b8d0f413ba9096463286541c8ed90e9b05ccc8
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Thu Jun 5 22:45:35 2014 +0200

    lenovo/x60/i915.c: Place GTT below top of memory
    
    Since commit 17fec8a0 [1]
    
    	drm/i915: Use Graphics Base of Stolen Memory on all gen3+
    
    present in the Linux kernel since version 3.12, 3D does not work
    anymore [2].
    
    Comparing the graphics registers, in this case that means output of
    `intel_reg_dumper`, the vendor Video BIOS is setting the register
    PGTBL_CTL/PGETBL_CTL, only documented in the i965 datasheet [3], to
    `0x3ffc0001` on a system with 1 GB of RAM, while native graphics init
    sets it to `0x3f800001`.
    
    Currently native graphis init sets the GTT right above the base
    address of stolen memory. The Video BIOS sets it below the top of
    memory.  The Linux Intel driver expects it to be below top of memory, so
    do it this way, by setting the address to TOM minus the size of the GTT,
    which is hardcoded to 256 KiB.
    
    As `PGETBL_CTL` is zero by default, reading its value in the beginning
    is not necessary and is only confusing. Make it clear that the code
    calculates the value.
    
    There is still an error PTE error reported during boot, but 3D works
    with Linux 3.12+ and no user visible problems are shown.
    
    [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=17fec8a08698bcab98788e1e89f5b8e7502ababd
    [2] https://bugs.freedesktop.org/show_bug.cgi?id=79038
    [3] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_1_graphics_core_0.pdf
        Intel ® 965 Express Chipset Family and
          Intel ® G35 Express Chipset Graphics Controller
          Programmer’s Reference Manual
        Volume 1: Graphics Core
        Revision 1.0a
    
    Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 src/mainboard/lenovo/x60/i915.c     | 16 ++++++++++++----
 src/mainboard/lenovo/x60/i915_reg.h |  2 ++
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c
index 529b262..129b89c 100644
--- a/src/mainboard/lenovo/x60/i915.c
+++ b/src/mainboard/lenovo/x60/i915.c
@@ -135,11 +135,19 @@ int gtt_setup(unsigned int mmiobase);
 int gtt_setup(unsigned int mmiobase)
 {
 	unsigned long PGETBL_save;
-
-	PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
+	unsigned long tom;
+
+	/*
+	 * The Video BIOS places the GTT right below top of memory.
+	 * It is not documented in the Intel 945 datasheet, but the Intel
+	 * developers said that it is normally placed there.
+	 *
+	 * TODO: Add option table value to make the GTT size runtime
+	 * configurable.
+	 */
+	tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
+	PGETBL_save = tom - 256 * KiB;
 	PGETBL_save |= PGETBL_ENABLED;
-
-	PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000;
 	PGETBL_save |= 2; /* set GTT to 256kb */
 
 	write32(mmiobase + GFX_FLSH_CNTL, 0);
diff --git a/src/mainboard/lenovo/x60/i915_reg.h b/src/mainboard/lenovo/x60/i915_reg.h
index 382b822..a12ba55 100644
--- a/src/mainboard/lenovo/x60/i915_reg.h
+++ b/src/mainboard/lenovo/x60/i915_reg.h
@@ -27,6 +27,8 @@
 
 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
 
+#define TOLUD 0x9c
+
 /*
  * The Bridge device's PCI config space has information about the
  * fb aperture size and the amount of pre-reserved memory.



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