[coreboot-gerrit] Patch merged into coreboot/master: 42b1b80 Exynos5420: ddr3: fine tuning the DDR3 timing values

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 42b1b8069c35a4e86772b600ea0264503bf20470
Author: David Hendricks <dhendrix at chromium.org>
Date:   Mon Aug 26 15:12:12 2013 -0700

    Exynos5420: ddr3: fine tuning the DDR3 timing values
    
    Fine tuning DDR timings value for better stability
    
    * Changed Data Driver Strength from 34 ohms to 30 ohms, expected to
      enhance signal integrity.
    * Changed DQ signal from 0xf to 0x1f000f, to keep default value safe.
    * Changed mrs[2] and added new mrs direct command for setting WL/RL
      without resetting DLL.
    * Added explicit reset value write in phy_con0 instead of just setting
      a bit, to ensure that reset happens.
    * Added DREX automatic control for ctrl_pd in none read memory state.
    
    This is ported from: https://gerrit.chromium.org/gerrit/61405
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    
    Change-Id: I59e96e6dede7b49c6572548aca664d82ad110bb1
    Reviewed-on: https://chromium-review.googlesource.com/66995
    Reviewed-by: ron minnich <rminnich at chromium.org>
    Commit-Queue: David Hendricks <dhendrix at chromium.org>
    Tested-by: David Hendricks <dhendrix at chromium.org>
    (cherry picked from commit ec34b711c6d270672c56d45c370ca14c0aa27ca3)
    Signed-off-by: Isaac Christensen <isaac.christensen at se-eng.com>
    Reviewed-on: http://review.coreboot.org/6611
    Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/6611 for details.

-gerrit