[coreboot-gerrit] New patch to review for coreboot: af441a2 gm45: Move S3 detection to enable stage.

[Vladimir Serbinenko (phcoder@gmail.com)]

Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6625

-gerrit

commit af441a2af630a71a0b0d8b97657aade6e331e9b6
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Tue Aug 12 09:07:13 2014 +0200

    gm45: Move S3 detection to enable stage.
    
    Also move it to NB to be in line with other.
    
    Change-Id: Ibd961d60dcd686899f34f6a494c14ff9d65e618b
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
 src/northbridge/intel/gm45/northbridge.c  | 18 ++++++++++++++++++
 src/southbridge/intel/i82801ix/i82801ix.c | 17 -----------------
 2 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index afac035..48a81c0 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -32,6 +32,7 @@
 #include <cbmem.h>
 #include "chip.h"
 #include "gm45.h"
+#include "arch/acpi.h"
 
 /* Reserve everything between A segment and 1MB:
  *
@@ -228,6 +229,23 @@ static void enable_dev(device_t dev)
 	} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
 		dev->ops = &cpu_bus_ops;
 	}
+
+#if CONFIG_HAVE_ACPI_RESUME
+	switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) {
+	case SKPAD_NORMAL_BOOT_MAGIC:
+		printk(BIOS_DEBUG, "Normal boot.\n");
+		acpi_slp_type=0;
+		break;
+	case SKPAD_ACPI_S3_MAGIC:
+		printk(BIOS_DEBUG, "S3 Resume.\n");
+		acpi_slp_type=3;
+		break;
+	default:
+		printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
+		acpi_slp_type=0;
+		break;
+	}
+#endif
 }
 
 static void gm45_init(void *const chip_info)
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c
index 0fe7d20..1894a30 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.c
+++ b/src/southbridge/intel/i82801ix/i82801ix.c
@@ -234,23 +234,6 @@ static void i82801ix_init(void *chip_info)
 	outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */
 #endif
 	outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */
-
-#if CONFIG_HAVE_ACPI_RESUME
-	switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) {
-	case SKPAD_NORMAL_BOOT_MAGIC:
-		printk(BIOS_DEBUG, "Normal boot.\n");
-		acpi_slp_type=0;
-		break;
-	case SKPAD_ACPI_S3_MAGIC:
-		printk(BIOS_DEBUG, "S3 Resume.\n");
-		acpi_slp_type=3;
-		break;
-	default:
-		printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
-		acpi_slp_type=0;
-		break;
-	}
-#endif
 }
 
 struct chip_operations southbridge_intel_i82801ix_ops = {