[coreboot-gerrit] New patch to review for coreboot: e83e5ec cpu/amd/geode_lx: Reduce fancy ASCII art with embedded comments

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6550

-gerrit

commit e83e5ecf2b99391ff76b7d050a7ffc72364b9cb7
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sat Aug 9 15:51:19 2014 +1000

    cpu/amd/geode_lx: Reduce fancy ASCII art with embedded comments
    
    Lets try not to play games with the Lexer with fancy ASCII art. Doxygen
    has a more well defined and useful syntax for annotations.
    
    Change-Id: I6f6c58971f509064ae1e28a1740e50e2ae721513
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/cpu/amd/geode_lx/cache_as_ram.inc | 11 +++++------
 src/cpu/amd/geode_lx/cpubug.c         | 28 +++++++++++++---------------
 src/cpu/amd/geode_lx/cpureginit.c     | 14 ++------------
 src/cpu/amd/geode_lx/syspreinit.c     | 16 +++++++---------
 4 files changed, 27 insertions(+), 42 deletions(-)

diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc
index db95dee..73281a3 100644
--- a/src/cpu/amd/geode_lx/cache_as_ram.inc
+++ b/src/cpu/amd/geode_lx/cache_as_ram.inc
@@ -25,15 +25,14 @@
 #define	LX_CACHEWAY_SIZE	(LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
 #define	CR0_CD				0x40000000	/* bit 30 = Cache Disable */
 #define	CR0_NW				0x20000000	/* bit 29 = Not Write Through */
+
 #include <cpu/amd/lxdef.h>
 #include <cpu/x86/post_code.h>
-/***************************************************************************
-/**
-/**	DCacheSetup
-/**
-/**	Setup data cache for  use as RAM for a stack.
+
 /**
-/***************************************************************************/
+ *	DCacheSetup
+ *	Setup data cache for  use as RAM for a stack.
+ */
 DCacheSetup:
 	/* Save the BIST result */
 	movl    %eax, %ebx
diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c
index ebadec7..acf176a 100644
--- a/src/cpu/amd/geode_lx/cpubug.c
+++ b/src/cpu/amd/geode_lx/cpubug.c
@@ -29,15 +29,15 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/lxdef.h>
 
-/**************************************************************************
+/**
  *
  *	pcideadlock
  *
  *	Bugtool #465 and #609
  *	PCI cache deadlock
- *	There is also fix code in cache and PCI functions. This bug is very is pervasive.
- *
- **************************************************************************/
+ *	There is also fix code in cache and PCI functions.
+ *	This bug is very is pervasive.
+ */
 static void pcideadlock(void)
 {
 	msr_t msr;
@@ -61,17 +61,15 @@ static void pcideadlock(void)
 	wrmsr(CPU_RCONF_E0_FF, msr);
 }
 
-/****************************************************************************/
-/***/
-/**	DisableMemoryReorder*/
-/***/
-/**	PBZ 3659:*/
-/**	 The MC reordered transactions incorrectly and breaks coherency.*/
-/**	 Disable reordering and take a potential performance hit.*/
-/**	 This is safe to do here and not in MC init since there is nothing*/
-/**	 to maintain coherency with and the cache is not enabled yet.*/
-/***/
-/****************************************************************************/
+/**
+ *	DisableMemoryReorder
+ *
+ *	PBZ 3659:
+ *	 The MC reordered transactions incorrectly and breaks coherency.
+ *	 Disable reordering and take a potential performance hit.
+ *	 This is safe to do here and not in MC init since there is nothing
+ *	 to maintain coherency with and the cache is not enabled yet.
+ */
 static void disablememoryreadorder(void)
 {
 	msr_t msr;
diff --git a/src/cpu/amd/geode_lx/cpureginit.c b/src/cpu/amd/geode_lx/cpureginit.c
index 30d9595..79e0a70 100644
--- a/src/cpu/amd/geode_lx/cpureginit.c
+++ b/src/cpu/amd/geode_lx/cpureginit.c
@@ -20,16 +20,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/**************************************************************************
-;*
-;*	SetDelayControl
-;*
-;*************************************************************************/
+/* SetDelayControl */
 #include "cpu/x86/msr.h"
 
 
-
-
 /**
  * Delay Control Settings table from AMD (MCP 0x4C00000F).
  */
@@ -39,8 +33,6 @@ static const msrinit_t delay_msr_table[] = {
 	{CPU_BC_MSS_ARRAY_CTL2, {.hi = 0x00000106, .lo = 0x83104104}},
 };
 
-
-
 static const struct delay_controls {
 	u8 dimms;
 	u8 devices;
@@ -171,9 +163,7 @@ static void SetDelayControl(u8 dimm0, u8 dimm1, int terminated)
 	wrmsr(GLCP_DELAY_CONTROLS, msr);
 }
 
-/* ***************************************************************************/
-/* *	cpuRegInit*/
-/* ***************************************************************************/
+/* cpuRegInit */
 void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)
 {
 	int msrnum;
diff --git a/src/cpu/amd/geode_lx/syspreinit.c b/src/cpu/amd/geode_lx/syspreinit.c
index a6979d7..1dcaebb 100644
--- a/src/cpu/amd/geode_lx/syspreinit.c
+++ b/src/cpu/amd/geode_lx/syspreinit.c
@@ -20,15 +20,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/* ***************************************************************************/
-/* **/
-/* *	StartTimer1*/
-/* **/
-/* *	Entry: none*/
-/* *	Exit: Starts Timer 1 for port 61 use*/
-/* *	Destroys: Al,*/
-/* **/
-/* ***************************************************************************/
+/**
+ *	StartTimer1
+ *
+ *	Entry: none
+ *	Exit: Starts Timer 1 for port 61 use
+ *	Destroys: Al,
+ */
 static void StartTimer1(void)
 {
 	outb(0x56, 0x43);