[coreboot-gerrit] Patch set updated for coreboot: 5134ff1 Provide helpers for read/modify/write access to registers

[Patrick Georgi (patrick@georgi-clan.de)]

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6492

-gerrit

commit 5134ff187ba533eb695597007a7d869a1cee24b1
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Mon Aug 4 17:17:24 2014 +0200

    Provide helpers for read/modify/write access to registers
    
    These are provided for IO, memory access and PCI config space
    
    Change-Id: I491d857fe68f2bbd3de9deb3fd05c5c193378bbe
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/arch/x86/include/arch/io.h | 22 ++++++++++++++++++++++
 src/include/device/pci_ops.h   | 39 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 61 insertions(+)

diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index b6d82f9..4479f58 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -77,6 +77,15 @@ static inline uint32_t inl(uint16_t port)
 	__asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port));
 	return value;
 }
+
+static inline void rmw_io16(uint16_t port, uint16_t mask, uint16_t val)
+{
+	uint16_t tmp = inw(port);
+	tmp &= mask;
+	tmp |= val;
+	outw(tmp, port);
+}
+
 #endif /* __ROMCC__ */
 
 static inline void outsb(uint16_t port, const void *addr, unsigned long count)
@@ -167,6 +176,19 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui
 	*((volatile uint32_t *)(addr)) = value;
 }
 
+static inline void rmw_mem32(unsigned long addr, uint32_t mask, uint32_t val)
+{
+	uint32_t tmp = read32(addr);
+	tmp &= mask;
+	tmp |= val;
+	write32(addr, tmp);
+}
+
+static inline void or_mem32(unsigned long addr, uint32_t val)
+{
+	rmw_mem32(addr, ~0, val);
+}
+
 /* Conflicts with definition in lib.h */
 #if defined(__ROMCC__) || defined(__SMM__)
 static inline int log2(int value)
diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h
index ae58a01..84b1a7d 100644
--- a/src/include/device/pci_ops.h
+++ b/src/include/device/pci_ops.h
@@ -13,6 +13,45 @@ void pci_write_config8(device_t dev, unsigned int where, u8 val);
 void pci_write_config16(device_t dev, unsigned int where, u16 val);
 void pci_write_config32(device_t dev, unsigned int where, u32 val);
 
+static inline void pci_rmw_config8(device_t dev, unsigned int reg, u8 mask, u8 val)
+{
+	u8 tmp = pci_read_config8(dev, reg);
+	tmp &= mask;
+	tmp |= val;
+	pci_write_config8(dev, reg, tmp);
+}
+
+static inline void pci_rmw_config16(device_t dev, unsigned int reg, u16 mask, u16 val)
+{
+	u16 tmp = pci_read_config16(dev, reg);
+	tmp &= mask;
+	tmp |= val;
+	pci_write_config16(dev, reg, tmp);
+}
+
+static inline void pci_rmw_config32(device_t dev, unsigned int reg, u32 mask, u32 val)
+{
+	u32 tmp = pci_read_config32(dev, reg);
+	tmp &= mask;
+	tmp |= val;
+	pci_write_config32(dev, reg, tmp);
+}
+
+static inline void pci_or_config8(device_t dev, unsigned int reg, u8 val)
+{
+	pci_rmw_config8(dev, reg, ~0, val);
+}
+
+static inline void pci_or_config16(device_t dev, unsigned int reg, u16 val)
+{
+	pci_rmw_config16(dev, reg, ~0, val);
+}
+
+static inline void pci_or_config32(device_t dev, unsigned int reg, u32 val)
+{
+	pci_rmw_config32(dev, reg, ~0, val);
+}
+
 #if CONFIG_MMCONF_SUPPORT
 u8 pci_mmio_read_config8(device_t dev, unsigned int where);
 u16 pci_mmio_read_config16(device_t dev, unsigned int where);