[coreboot-gerrit] New patch to review for coreboot: 2d0d654 sandy/ivybridge: Make UMA size configurable.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Sun Aug 3 02:01:14 CEST 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6470
-gerrit
commit 2d0d654ab2c3cf875e88eb330028b78f36733dd7
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Sun Aug 3 01:59:38 2014 +0200
sandy/ivybridge: Make UMA size configurable.
Change-Id: I9aa3652d1b92cece01d024e19bdc065797896001
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/google/butterfly/cmos.layout | 13 ++++++++++++-
src/mainboard/google/link/cmos.layout | 13 ++++++++++++-
src/mainboard/google/parrot/cmos.layout | 13 ++++++++++++-
src/mainboard/google/stout/cmos.layout | 13 ++++++++++++-
src/mainboard/intel/emeraldlake2/cmos.layout | 14 +++++++++++++-
src/mainboard/kontron/ktqm77/cmos.layout | 12 +++++++++++-
src/mainboard/lenovo/t520/cmos.layout | 12 +++++++++++-
src/mainboard/lenovo/t530/cmos.layout | 12 +++++++++++-
src/mainboard/lenovo/x230/cmos.layout | 13 ++++++++++++-
src/mainboard/samsung/lumpy/cmos.layout | 14 +++++++++++++-
src/mainboard/samsung/stumpy/cmos.layout | 13 ++++++++++++-
src/northbridge/intel/sandybridge/early_init.c | 9 +++++++--
12 files changed, 138 insertions(+), 13 deletions(-)
diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout
index 8270212..1445fc6 100644
--- a/src/mainboard/google/butterfly/cmos.layout
+++ b/src/mainboard/google/butterfly/cmos.layout
@@ -93,7 +93,11 @@ entries
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
-#544 440 r 0 unused
+
+# coreboot config options: northbridge
+544 5 e 11 gfx_uma_size
+
+#549 435 r 0 unused
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
@@ -137,6 +141,13 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout
index 2dfa156..cf09f36 100644
--- a/src/mainboard/google/link/cmos.layout
+++ b/src/mainboard/google/link/cmos.layout
@@ -91,7 +91,11 @@ entries
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
-#544 440 r 0 unused
+
+# coreboot config options: northbridge
+544 5 e 11 gfx_uma_size
+
+#549 435 r 0 unused
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
@@ -134,6 +138,13 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout
index 2dfa156..cf09f36 100644
--- a/src/mainboard/google/parrot/cmos.layout
+++ b/src/mainboard/google/parrot/cmos.layout
@@ -91,7 +91,11 @@ entries
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
-#544 440 r 0 unused
+
+# coreboot config options: northbridge
+544 5 e 11 gfx_uma_size
+
+#549 435 r 0 unused
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
@@ -134,6 +138,13 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout
index 2dfa156..cf09f36 100644
--- a/src/mainboard/google/stout/cmos.layout
+++ b/src/mainboard/google/stout/cmos.layout
@@ -91,7 +91,11 @@ entries
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
-#544 440 r 0 unused
+
+# coreboot config options: northbridge
+544 5 e 11 gfx_uma_size
+
+#549 435 r 0 unused
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
@@ -134,6 +138,13 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout
index 2dfa156..0e66b31 100644
--- a/src/mainboard/intel/emeraldlake2/cmos.layout
+++ b/src/mainboard/intel/emeraldlake2/cmos.layout
@@ -91,7 +91,11 @@ entries
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
-#544 440 r 0 unused
+
+# coreboot config options: northbridge
+544 5 e 11 gfx_uma_size
+
+#549 435 r 0 unused
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
@@ -134,6 +138,14 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout
index 245b47e..b7807aa 100644
--- a/src/mainboard/kontron/ktqm77/cmos.layout
+++ b/src/mainboard/kontron/ktqm77/cmos.layout
@@ -80,7 +80,9 @@ entries
# coreboot config options: cpu
400 1 e 2 hyper_threading
-#401 7 r 0 unused
+401 5 e 12 gfx_uma_size
+
+#406 2 r 0 unused
# coreboot config options: southbridge
408 1 e 1 nmi
@@ -165,6 +167,14 @@ enumerations
10 4 LM75 at 9e
11 0 AHCI
11 1 Compatible
+12 0 32M
+12 1 64M
+12 2 96M
+12 3 128M
+12 4 160M
+12 5 192M
+12 6 224M
+
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout
index 50aa5f3..db842c7 100644
--- a/src/mainboard/lenovo/t520/cmos.layout
+++ b/src/mainboard/lenovo/t520/cmos.layout
@@ -100,8 +100,11 @@ entries
# coreboot config options: cpu
424 1 e 2 hyper_threading
+#425 7 r 0 unused
-#425 559 r 0 unused
+# coreboot config options: northbridge
+432 5 e 11 gfx_uma_size
+#437 547 r 0 unused
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
@@ -150,6 +153,13 @@ enumerations
10 1 Keyboard only
10 2 Thinklight only
10 3 None
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout
index 50aa5f3..db842c7 100644
--- a/src/mainboard/lenovo/t530/cmos.layout
+++ b/src/mainboard/lenovo/t530/cmos.layout
@@ -100,8 +100,11 @@ entries
# coreboot config options: cpu
424 1 e 2 hyper_threading
+#425 7 r 0 unused
-#425 559 r 0 unused
+# coreboot config options: northbridge
+432 5 e 11 gfx_uma_size
+#437 547 r 0 unused
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
@@ -150,6 +153,13 @@ enumerations
10 1 Keyboard only
10 2 Thinklight only
10 3 None
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout
index 50aa5f3..98ca932 100644
--- a/src/mainboard/lenovo/x230/cmos.layout
+++ b/src/mainboard/lenovo/x230/cmos.layout
@@ -100,8 +100,11 @@ entries
# coreboot config options: cpu
424 1 e 2 hyper_threading
+#425 7 r 0 unused
-#425 559 r 0 unused
+# coreboot config options: northbridge
+432 5 e 11 gfx_uma_size
+#437 547 r 0 unused
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
@@ -150,6 +153,14 @@ enumerations
10 1 Keyboard only
10 2 Thinklight only
10 3 None
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout
index 9f0e9f3..440eb2f 100644
--- a/src/mainboard/samsung/lumpy/cmos.layout
+++ b/src/mainboard/samsung/lumpy/cmos.layout
@@ -91,7 +91,11 @@ entries
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
-#544 440 r 0 unused
+
+# coreboot config options: northbridge
+544 5 e 11 gfx_uma_size
+
+#549 435 r 0 unused
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
@@ -134,6 +138,14 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout
index e7b73a2..55284a5 100644
--- a/src/mainboard/samsung/stumpy/cmos.layout
+++ b/src/mainboard/samsung/stumpy/cmos.layout
@@ -90,7 +90,11 @@ entries
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
-#544 440 r 0 unused
+
+# coreboot config options: northbridge
+544 5 e 11 gfx_uma_size
+
+#549 435 r 0 unused
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
@@ -134,6 +138,13 @@ enumerations
7 2 Keep
8 0 AHCI
8 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
# -----------------------------------------------------------------
checksums
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index d688f5b..d1d35db 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -24,6 +24,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <elog.h>
+#include <pc80/mc146818rtc.h>
#include "sandybridge.h"
static void sandybridge_setup_bars(void)
@@ -83,6 +84,7 @@ static void sandybridge_setup_graphics(void)
u32 reg32;
u16 reg16;
u8 reg8;
+ u8 gfxsize;
reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID);
switch (reg16) {
@@ -103,10 +105,13 @@ static void sandybridge_setup_graphics(void)
printk(BIOS_DEBUG, "Initializing Graphics...\n");
- /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
+ if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
+ /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
+ gfxsize = 0;
+ }
reg16 = pci_read_config16(PCI_DEV(0,0,0), GGC);
reg16 &= ~0x00f8;
- reg16 |= 1 << 3;
+ reg16 |= (gfxsize + 1) << 3;
/* Program GTT memory by setting GGC[9:8] = 2MB */
reg16 &= ~0x0300;
reg16 |= 2 << 8;
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