[coreboot-gerrit] New patch to review for coreboot: f1604d7 'chip.h': Add missing header guards
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Fri Aug 1 14:59:44 CEST 2014
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6453
-gerrit
commit f1604d786efaf050a747fd73c3c35879968f4c4c
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Fri Aug 1 14:59:28 2014 +0200
'chip.h': Add missing header guards
Change-Id: I286788a7c22e8c49b07e4135457bbbfb39ebc32e
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/supermicro/h8scm/chip.h | 4 ++++
src/northbridge/intel/e7520/chip.h | 5 +++++
src/northbridge/intel/e7525/chip.h | 5 +++++
src/northbridge/intel/fsp_sandybridge/chip.h | 5 +++++
src/northbridge/intel/haswell/chip.h | 5 +++++
src/northbridge/intel/i3100/chip.h | 5 +++++
src/northbridge/intel/nehalem/chip.h | 5 +++++
src/northbridge/intel/sandybridge/chip.h | 5 +++++
src/northbridge/via/vx900/chip.h | 5 +++++
src/southbridge/intel/esb6300/chip.h | 5 +++++
src/southbridge/intel/i3100/chip.h | 5 +++++
11 files changed, 54 insertions(+)
diff --git a/src/mainboard/supermicro/h8scm/chip.h b/src/mainboard/supermicro/h8scm/chip.h
index df1ae35..5f1a40c 100644
--- a/src/mainboard/supermicro/h8scm/chip.h
+++ b/src/mainboard/supermicro/h8scm/chip.h
@@ -17,7 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef CHIP_H
+#define CHIP_H
extern struct chip_operations mainboard_ops;
struct mainboard_config {};
+
+#endif /* CHIP_H */
diff --git a/src/northbridge/intel/e7520/chip.h b/src/northbridge/intel/e7520/chip.h
index 2b9e196..b497059 100644
--- a/src/northbridge/intel/e7520/chip.h
+++ b/src/northbridge/intel/e7520/chip.h
@@ -1,5 +1,10 @@
+#ifndef CHIP_H
+#define CHIP_H
+
struct northbridge_intel_e7520_config
{
/* Interrupt line connect */
unsigned int intrline;
};
+
+#endif /* CHIP_H */
diff --git a/src/northbridge/intel/e7525/chip.h b/src/northbridge/intel/e7525/chip.h
index c98555c..33e6d94 100644
--- a/src/northbridge/intel/e7525/chip.h
+++ b/src/northbridge/intel/e7525/chip.h
@@ -1,5 +1,10 @@
+#ifndef CHIP_H
+#define CHIP_H
+
struct northbridge_intel_e7525_config
{
/* Interrupt line connect */
unsigned int intrline;
};
+
+#endif /* CHIP_H */
diff --git a/src/northbridge/intel/fsp_sandybridge/chip.h b/src/northbridge/intel/fsp_sandybridge/chip.h
index 9b5f605..5916db2 100644
--- a/src/northbridge/intel/fsp_sandybridge/chip.h
+++ b/src/northbridge/intel/fsp_sandybridge/chip.h
@@ -17,6 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef CHIP_H
+#define CHIP_H
+
/*
* Digital Port Hotplug Enable:
* 0x04 = Enabled, 2ms short pulse
@@ -39,3 +42,5 @@ struct northbridge_intel_fsp_sandybridge_config {
u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
u32 gpu_pch_backlight; /* PCH Backlight PWM value */
};
+
+#endif /* CHIP_H */
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h
index d60504c..8be50d6 100644
--- a/src/northbridge/intel/haswell/chip.h
+++ b/src/northbridge/intel/haswell/chip.h
@@ -17,6 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef CHIP_H
+#define CHIP_H
+
/*
* Digital Port Hotplug Enable:
* 0x04 = Enabled, 2ms short pulse
@@ -41,3 +44,5 @@ struct northbridge_intel_haswell_config {
};
extern struct chip_operations northbridge_intel_haswell_ops;
+
+#endif /* CHIP_H */
diff --git a/src/northbridge/intel/i3100/chip.h b/src/northbridge/intel/i3100/chip.h
index ca76b02..8034f18 100644
--- a/src/northbridge/intel/i3100/chip.h
+++ b/src/northbridge/intel/i3100/chip.h
@@ -17,8 +17,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef CHIP_H
+#define CHIP_H
+
struct northbridge_intel_i3100_config
{
/* Interrupt line connect */
u16 intrline;
};
+
+#endif /* CHIP_H */
diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h
index e33d108..dea87e7 100644
--- a/src/northbridge/intel/nehalem/chip.h
+++ b/src/northbridge/intel/nehalem/chip.h
@@ -17,6 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef CHIP_H
+#define CHIP_H
+
/*
* Digital Port Hotplug Enable:
* 0x04 = Enabled, 2ms short pulse
@@ -44,3 +47,5 @@ struct northbridge_intel_nehalem_config {
int gpu_link_frequency_270_mhz;
int gpu_lvds_num_lanes;
};
+
+#endif /* CHIP_H */
diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h
index cc32c37..9ef72e2 100644
--- a/src/northbridge/intel/sandybridge/chip.h
+++ b/src/northbridge/intel/sandybridge/chip.h
@@ -17,6 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef CHIP_H
+#define CHIP_H
+
/*
* Digital Port Hotplug Enable:
* 0x04 = Enabled, 2ms short pulse
@@ -44,3 +47,5 @@ struct northbridge_intel_sandybridge_config {
int gpu_link_frequency_270_mhz;
int gpu_lvds_num_lanes;
};
+
+#endif /* CHIP_H */
diff --git a/src/northbridge/via/vx900/chip.h b/src/northbridge/via/vx900/chip.h
index 6334a8e..fb47582 100644
--- a/src/northbridge/via/vx900/chip.h
+++ b/src/northbridge/via/vx900/chip.h
@@ -17,6 +17,9 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#ifndef CHIP_H
+#define CHIP_H
+
struct northbridge_via_vx900_config {
/**
* \brief PCIe Lane[3:0] Function Select
@@ -50,3 +53,5 @@ struct northbridge_via_vx900_config {
*/
char ext_int_route_to_pirq;
};
+
+#endif /* CHIP_H */
diff --git a/src/southbridge/intel/esb6300/chip.h b/src/southbridge/intel/esb6300/chip.h
index 384a991..6e6b842 100644
--- a/src/southbridge/intel/esb6300/chip.h
+++ b/src/southbridge/intel/esb6300/chip.h
@@ -1,3 +1,6 @@
+#ifndef CHIP_H
+#define CHIP_H
+
struct southbridge_intel_esb6300_config
{
#define ESB6300_GPIO_USE_MASK 0x03
@@ -26,3 +29,5 @@ struct southbridge_intel_esb6300_config
unsigned int pirq_a_d;
unsigned int pirq_e_h;
};
+
+#endif /* CHIP_H */
diff --git a/src/southbridge/intel/i3100/chip.h b/src/southbridge/intel/i3100/chip.h
index b0f3f32..5fb4d56 100644
--- a/src/southbridge/intel/i3100/chip.h
+++ b/src/southbridge/intel/i3100/chip.h
@@ -18,6 +18,9 @@
*
*/
+#ifndef CHIP_H
+#define CHIP_H
+
struct southbridge_intel_i3100_config
{
#define I3100_GPIO_USE_MASK 0x03
@@ -47,3 +50,5 @@ struct southbridge_intel_i3100_config
u32 pirq_a_d;
u32 pirq_e_h;
};
+
+#endif /* CHIP_H */
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