[coreboot-gerrit] Patch set updated for coreboot: 994d0fc bayleybay_fsp: Add bakersport board variant

[Martin Roth (gaumless@gmail.com)]

Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5983

-gerrit

commit 994d0fc2f3464152048d6d97acab83205ed79747
Author: Martin Roth <martin.roth at se-eng.com>
Date:   Thu Jun 12 12:08:26 2014 -0600

    bayleybay_fsp: Add bakersport board variant
    
    The Bakersport board is a variant of the Bayley Bay mainboard that uses
    one ECC DIMM instead of two non-ECC dimms.
    
    This commit uses the Bayley Bay mainboard directory and modifies the
    required pieces to add the Bakersport board variant.  It disables the
    second DIMM, points to an ECC version of the FSP, and sets the board
    name to be Bakersport instead of Bayley Bay.
    
    All of the code is still contained in the bayleybay_fsp directory.  It
    seems like duplicating the whole directory for the one line of code
    that's actually different between the two platforms.
    
    Change-Id: Ia31e9ee927a6810a01a1ae143fcb00cfb7d8a7aa
    Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
 src/mainboard/intel/Kconfig                   |   3 +
 src/mainboard/intel/bakersport_fsp/Kconfig    | 103 ++++++++++++++++++++++++++
 src/mainboard/intel/bakersport_fsp/readme.txt |   5 ++
 src/mainboard/intel/bayleybay_fsp/romstage.c  |   5 ++
 4 files changed, 116 insertions(+)

diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig
index 4f1ff4c..4578dfe 100644
--- a/src/mainboard/intel/Kconfig
+++ b/src/mainboard/intel/Kconfig
@@ -3,6 +3,8 @@ if VENDOR_INTEL
 choice
 	prompt "Mainboard model"
 
+config BOARD_INTEL_BAKERSPORT_FSP
+	bool "Bakersport FSP-based CRB"
 config BOARD_INTEL_BAYLEYBAY_FSP
 	bool "Bayley Bay FSP-based CRB"
 config BOARD_INTEL_COUGAR_CANYON2
@@ -32,6 +34,7 @@ config BOARD_INTEL_WTM2
 
 endchoice
 
+source "src/mainboard/intel/bakersport_fsp/Kconfig"
 source "src/mainboard/intel/bayleybay_fsp/Kconfig"
 source "src/mainboard/intel/cougar_canyon2/Kconfig"
 source "src/mainboard/intel/d810e2cb/Kconfig"
diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig
new file mode 100644
index 0000000..043e98a
--- /dev/null
+++ b/src/mainboard/intel/bakersport_fsp/Kconfig
@@ -0,0 +1,103 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_INTEL_BAKERSPORT_FSP
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select SOC_INTEL_FSP_BAYTRAIL
+	select BOARD_ROMSIZE_KB_2048
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select OVERRIDE_MRC_CACHE_LOC
+	select POST_IO
+	select INCLUDE_MICROCODE_IN_BUILD if FSP_PACKAGE_DEFAULT
+	select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
+	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
+	select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT
+	select TSC_MONOTONIC_TIMER
+
+config MAINBOARD_DIR
+	string
+	default "intel/bayleybay_fsp"
+
+config INCLUDE_ME
+	bool
+	default n
+
+config LOCK_MANAGEMENT_ENGINE
+	bool
+	default n
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Bakersport CRB"
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 16
+
+config CACHE_ROM_SIZE_OVERRIDE
+	hex
+	default 0x800000
+
+config FSP_FILE
+	string
+	default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP
+
+config MRC_CACHE_LOC_OVERRIDE
+	hex
+	default 0xfff80000
+	depends on ENABLE_FSP_FAST_BOOT
+
+config CBFS_SIZE
+	hex
+	default 0x00200000
+
+config DRIVERS_PS2_KEYBOARD
+	bool
+	default n
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ENABLE_FSP_FAST_BOOT
+	bool
+	depends on HAVE_FSP_BIN
+	default y
+
+config VIRTUAL_ROM_SIZE
+	hex
+	depends on ENABLE_FSP_FAST_BOOT
+	default 0x800000
+
+config FSP_PACKAGE_DEFAULT
+	bool "Configure defaults for the Intel FSP package"
+	default n
+
+config VGA_BIOS
+	bool
+	default y if FSP_PACKAGE_DEFAULT
+
+endif # BOARD_INTEL_BAKERSPORT_FSP
diff --git a/src/mainboard/intel/bakersport_fsp/readme.txt b/src/mainboard/intel/bakersport_fsp/readme.txt
new file mode 100644
index 0000000..b76592c
--- /dev/null
+++ b/src/mainboard/intel/bakersport_fsp/readme.txt
@@ -0,0 +1,5 @@
+The code for the bakersport board is in the bayleybay_fsp directory.
+
+This directory is just here so so that the bakersport board gets built by
+abuild and so that there is a separate entry in the wiki and board-status
+tree.
diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c
index 34199bd..ef848fa 100644
--- a/src/mainboard/intel/bayleybay_fsp/romstage.c
+++ b/src/mainboard/intel/bayleybay_fsp/romstage.c
@@ -173,4 +173,9 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
 
 	/* Initialize the Azalia Verb Tables to mainboard specific version */
 	UpdData->AzaliaConfigPtr  = (UINT32)&mainboard_AzaliaConfig;
+
+	/* Disable 2nd DIMM on Bakersport*/
+#if IS_ENABLED(BOARD_INTEL_BAKERSPORT_FSP)
+	UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */
+#endif
 }