[coreboot-gerrit] Patch merged into coreboot/master: 6b583a4 vendorcode/amd/agesa: Do not hardcode ROM base address

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 6b583a454c24c0c8fb41da9eaef52a830e83b3e4
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Sun Apr 6 15:19:56 2014 -0500

    vendorcode/amd/agesa: Do not hardcode ROM base address
    
    The ROM address range is set up in the LPC PCI device, register 0x6c.
    Coreboot already sets that up correctly in the bootblock, however
    AGESA overrides that to 0xffffff00, which will always map the ROM from
    0xff000000. This may conflict with other devices which are assigned
    address space in that range.
    
    If a device is assigned a range between 0xff000000 and the real ROM
    base, accesses to that device will be diverted to the system ROM,
    regardless of how other BARs are set up. Since we already need to set
    up the ROM address range in the bootblock, before calling AGESA, just
    remove the override from AGESA.
    
    Note that not all AGESA versions override this mapping.
    
    Change-Id: I592e5d087ed830c9604a04a356912c7654ce56d2
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-on: http://review.coreboot.org/5467
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
    Reviewed-by: Aaron Durbin <adurbin at google.com>


See http://review.coreboot.org/5467 for details.

-gerrit