[coreboot-gerrit] Patch set updated for coreboot: 0af9da9 superio/ite/it8712f: Avoid .c includes
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Tue Apr 8 15:04:06 CEST 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5476
-gerrit
commit 0af9da9459ac45c0e413a364e8f25cd8c696870f
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Tue Apr 8 17:26:11 2014 +1000
superio/ite/it8712f: Avoid .c includes
NOTFORMERGE
Following the same reasoning as commit
d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid
.c includes
Clean up the early_serial #include directives in mainboard/romstage code.
This however requires a major re-write of superio/ite/it8712f.
Change-Id: I502d59671fa2888a43eb473af618ea46ad237aa7
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/mainboard/amd/dbm690t/romstage.c | 2 +-
src/mainboard/amd/pistachio/romstage.c | 2 +-
src/mainboard/asus/a8n_e/romstage.c | 5 +-
src/mainboard/asus/f2a85-m/romstage.c | 12 ++--
src/mainboard/asus/m2v-mx_se/romstage.c | 7 +-
src/mainboard/asus/m2v/romstage.c | 36 ++++++++--
src/mainboard/asus/m4a78-em/romstage.c | 9 ++-
src/mainboard/asus/m4a785-m/romstage.c | 9 ++-
src/mainboard/ecs/p6iwp-fe/romstage.c | 9 ++-
src/mainboard/lippert/hurricane-lx/romstage.c | 22 +++++-
src/mainboard/lippert/literunner-lx/romstage.c | 22 +++++-
src/mainboard/lippert/roadrunner-lx/romstage.c | 22 +++++-
src/mainboard/lippert/spacerunner-lx/romstage.c | 22 +++++-
src/mainboard/siemens/sitemp_g1p1/romstage.c | 10 +--
src/mainboard/technexion/tim5690/romstage.c | 10 +--
src/mainboard/technexion/tim8690/romstage.c | 9 ++-
src/superio/ite/it8712f/Makefile.inc | 2 +-
src/superio/ite/it8712f/chip.h | 2 +-
src/superio/ite/it8712f/early_serial.c | 91 ++++++++++++-------------
src/superio/ite/it8712f/it8712f.h | 9 +--
20 files changed, 218 insertions(+), 94 deletions(-)
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 74b6d1b..8f07d4e 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -35,7 +35,7 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include <spd.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 2971072..9953fff 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -30,7 +30,7 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include <spd.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index 29f425a..a1e6590 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -23,6 +23,7 @@
/* Used by it8712f_enable_serial(). */
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
#include <stdint.h>
#include <string.h>
@@ -33,7 +34,7 @@
#include <pc80/mc146818rtc.h>
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -103,7 +104,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- it8712f_24mhz_clkin();
+ it8712f_24mhz_clkin(CLKIN_DEV);
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index bc7546c..3a95ef9 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -35,10 +35,14 @@
#include <southbridge/amd/agesa/hudson/smbus.h>
#include <stdint.h>
#include <string.h>
+#include <superio/ite/it8712f/it8712f.h>
/* TODO: remove .c includes */
#include <drivers/pc80/i8254.c>
#include <drivers/pc80/i8259.c>
-#include <superio/ite/it8712f/early_serial.c>
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+#define VSBSW_DEV PNP_DEV(0x2e, IT8712F_GPIO)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
void disable_cache_as_ram(void);
@@ -88,9 +92,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* enable SIO clock */
sbxxx_enable_48mhzout();
- it8712f_kill_watchdog();
- it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
- it8712f_enable_3vsbsw();
+ it8712f_kill_watchdog(WATCHDOG_DEV);
+ it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ it8712f_enable_3vsbsw(VSBSW_DEV);
console_init();
/* turn on secondary smbus at b20 */
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index ef0ce87..4266fc3 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -38,7 +38,7 @@ unsigned int get_sbdn(unsigned bus);
#include "lib/delay.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "southbridge/via/vt8237r/early_smbus.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -46,6 +46,7 @@ unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+#define VSBSW_DEV PNP_DEV(0x2e, IT8712F_GPIO)
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -128,8 +129,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = &sysinfo_car;
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- it8712f_kill_watchdog();
- it8712f_enable_3vsbsw();
+ it8712f_kill_watchdog(WATCHDOG_DEV);
+ it8712f_enable_3vsbsw(VSBSW_DEV);
console_init();
enable_rom_decode();
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 1ca145d..6ba8307 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -38,7 +38,7 @@ unsigned int get_sbdn(unsigned bus);
#include "lib/delay.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "southbridge/via/vt8237r/early_smbus.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -46,6 +46,8 @@ unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+#define VSBSW_DEV PNP_DEV(0x2e, IT8712F_GPIO)
#define IT8712F_GPIO_BASE 0x0a20
@@ -125,6 +127,32 @@ static const struct gpio_init_val gpio_init_data[] = {
{ 0, 0 },
};
+static void it8712f_enter_conf(void)
+{
+ u16 port = 0x2e;
+
+ outb(0x87, port);
+ outb(0x01, port);
+ outb(0x55, port);
+ outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void it8712f_exit_conf(void)
+{
+ outb(0x07, 0x2e);
+ outb(0x00, 0x2f);
+ outb(0x02, 0x2e);
+ outb(0x02, 0x2f);
+}
+
+static void it8712f_sio_write(u8 ldn, u8 index, u8 value)
+{
+ outb(0x07, 0x2e);
+ outb(ldn, 0x2f);
+ outb(index, 0x2e);
+ outb(value, 0x2f);
+}
+
static void m2v_it8712f_gpio_init(void)
{
const struct gpio_init_val *giv;
@@ -225,14 +253,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset = 0;
struct sys_info *sysinfo = &sysinfo_car;
- it8712f_24mhz_clkin();
+ it8712f_24mhz_clkin(CLKIN_DEV);
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- it8712f_kill_watchdog();
+ it8712f_kill_watchdog(WATCHDOG_DEV);
console_init();
enable_rom_decode();
m2v_bus_init();
m2v_it8712f_gpio_init();
- it8712f_enable_3vsbsw();
+ it8712f_enable_3vsbsw(VSBSW_DEV);
printk(BIOS_INFO, "now booting... \n");
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 18c6f18..ca91f0d 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -41,7 +41,7 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
@@ -67,6 +67,9 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;
@@ -95,8 +98,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
- it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
- it8712f_kill_watchdog();
+ it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ it8712f_kill_watchdog(WATCHDOG_DEV);
console_init();
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 660ab0f..f6f6f3f 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -41,7 +41,7 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
@@ -49,6 +49,9 @@
#include "southbridge/amd/sb700/smbus.h"
#include "northbridge/amd/amdfam10/debug.c"
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
@@ -95,8 +98,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb7xx_51xx_lpc_init();
- it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
- it8712f_kill_watchdog();
+ it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ it8712f_kill_watchdog(WATCHDOG_DEV);
console_init();
diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c
index 1ebdedd..8f5626d 100644
--- a/src/mainboard/ecs/p6iwp-fe/romstage.c
+++ b/src/mainboard/ecs/p6iwp-fe/romstage.c
@@ -30,13 +30,16 @@
#include "northbridge/intel/i82810/raminit.h"
#include "drivers/pc80/udelay_io.c"
#include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include <lib.h>
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
void main(unsigned long bist)
{
- it8712f_24mhz_clkin();
- it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
+ it8712f_24mhz_clkin(CLKIN_DEV);
+ it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
report_bist_failure(bist);
enable_smbus();
diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index 95ea27d..3df271b 100644
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -35,7 +35,7 @@
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "northbridge/amd/lx/raminit.h"
/* Bit0 enables Spread Spectrum. */
@@ -95,10 +95,30 @@ static const u16 sio_init_table[] = { // hi=data, lo=index
#endif
};
+static void it8712f_enter_conf(void)
+{
+ u16 port = 0x2e;
+
+ outb(0x87, port);
+ outb(0x01, port);
+ outb(0x55, port);
+ outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void it8712f_exit_conf(void)
+{
+ outb(0x07, 0x2e);
+ outb(0x00, 0x2f);
+ outb(0x02, 0x2e);
+ outb(0x02, 0x2f);
+}
+
/* Early mainboard specific GPIO setup. */
static void mb_gpio_init(void)
{
int i;
+#define SIO_INDEX 0x2e
+#define SIO_DATA 0x2f
/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
it8712f_enter_conf();
diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index 6edcf37..56a1249 100644
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -35,7 +35,7 @@
#include "southbridge/amd/cs5536/cs5536.h"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "northbridge/amd/lx/raminit.h"
/* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */
@@ -137,10 +137,30 @@ static const u16 sio_init_table[] = { // hi=data, lo=index
0x08F8, // map GP LED Blinking 1 to GP10=LIVE_LED (deactivate Simple I/O to use)
};
+static void it8712f_enter_conf(void)
+{
+ u16 port = 0x2e;
+
+ outb(0x87, port);
+ outb(0x01, port);
+ outb(0x55, port);
+ outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void it8712f_exit_conf(void)
+{
+ outb(0x07, 0x2e);
+ outb(0x00, 0x2f);
+ outb(0x02, 0x2e);
+ outb(0x02, 0x2f);
+}
+
/* Early mainboard specific GPIO setup. */
static void mb_gpio_init(void)
{
int i;
+#define SIO_INDEX 0x2e
+#define SIO_DATA 0x2f
/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
it8712f_enter_conf();
diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index 68dcfc0..d5f0932 100644
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -35,7 +35,7 @@
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "northbridge/amd/lx/raminit.h"
int spd_read_byte(unsigned int device, unsigned int address)
@@ -70,10 +70,30 @@ static const u16 sio_init_table[] = { // hi=data, lo=index
0x0DF8, // map GP LED Blinking 1 to GP15=LIVE_LED (deactivate Simple-I/O to use)
};
+static void it8712f_enter_conf(void)
+{
+ u16 port = 0x2e;
+
+ outb(0x87, port);
+ outb(0x01, port);
+ outb(0x55, port);
+ outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void it8712f_exit_conf(void)
+{
+ outb(0x07, 0x2e);
+ outb(0x00, 0x2f);
+ outb(0x02, 0x2e);
+ outb(0x02, 0x2f);
+}
+
/* Early mainboard specific GPIO setup. */
static void mb_gpio_init(void)
{
int i;
+#define SIO_INDEX 0x2e
+#define SIO_DATA 0x2f
/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
it8712f_enter_conf();
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index 59bd618..2383da2 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -35,7 +35,7 @@
#include "southbridge/amd/cs5536/cs5536.h"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "northbridge/amd/lx/raminit.h"
/* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */
@@ -134,10 +134,30 @@ static const u16 sio_init_table[] = { // hi=data, lo=index
0x08F8, // map GP LED Blinking 1 to GP10=LIVE_LED (deactivate Simple I/O to use)
};
+static void it8712f_enter_conf(void)
+{
+ u16 port = 0x2e;
+
+ outb(0x87, port);
+ outb(0x01, port);
+ outb(0x55, port);
+ outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void it8712f_exit_conf(void)
+{
+ outb(0x07, 0x2e);
+ outb(0x00, 0x2f);
+ outb(0x02, 0x2e);
+ outb(0x02, 0x2f);
+}
+
/* Early mainboard specific GPIO setup. */
static void mb_gpio_init(void)
{
int i;
+#define SIO_INDEX 0x2e
+#define SIO_DATA 0x2f
/* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
it8712f_enter_conf();
diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c
index 6d36524..d3846ad 100644
--- a/src/mainboard/siemens/sitemp_g1p1/romstage.c
+++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c
@@ -43,7 +43,7 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "cpu/x86/bist.h"
@@ -84,6 +84,9 @@ static inline int spd_read_byte(u32 device, u32 address)
#define __DEBUG__(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg)
#define __INFO__(fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg)
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
@@ -111,9 +114,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0)
check_cmos(); // rebooting in case of corrupted cmos !!!!!
#endif
- /* it8712f_enable_serial does not use its 1st parameter. */
- it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
- it8712f_kill_watchdog();
+ it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ it8712f_kill_watchdog(WATCHDOG_DEV);
console_init();
#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1)
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index 42c2599..b9be934 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -37,7 +37,7 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/early_setup.c"
@@ -64,6 +64,9 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "speaker.c"
#include "northbridge/amd/amdk8/early_ht.c"
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
@@ -90,9 +93,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs690_dev8();
sb600_lpc_init();
- /* it8712f_enable_serial does not use its 1st parameter. */
- it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
- it8712f_kill_watchdog();
+ it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ it8712f_kill_watchdog(WATCHDOG_DEV);
console_init();
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 22a1212..3cf4def 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -37,7 +37,7 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/early_setup.c"
@@ -62,6 +62,9 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/early_ht.c"
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
@@ -86,8 +89,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb600_lpc_init();
/* it8712f_enable_serial does not use its 1st parameter. */
- it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
- it8712f_kill_watchdog();
+ it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ it8712f_kill_watchdog(WATCHDOG_DEV);
console_init();
diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc
index 3c8a512..ce75645 100644
--- a/src/superio/ite/it8712f/Makefile.inc
+++ b/src/superio/ite/it8712f/Makefile.inc
@@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c
-
diff --git a/src/superio/ite/it8712f/chip.h b/src/superio/ite/it8712f/chip.h
index 1f159cd..0354a8d 100644
--- a/src/superio/ite/it8712f/chip.h
+++ b/src/superio/ite/it8712f/chip.h
@@ -29,4 +29,4 @@ struct superio_ite_it8712f_config {
struct pc_keyboard keyboard;
};
-#endif
+#endif /* SUPERIO_ITE_IT8712F_CHIP_H */
diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c
index 51564fc..7a7a4b2 100644
--- a/src/superio/ite/it8712f/early_serial.c
+++ b/src/superio/ite/it8712f/early_serial.c
@@ -19,13 +19,9 @@
*/
#include <arch/io.h>
+#include <device/pnp.h>
#include "it8712f.h"
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE 0x2e
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
/* Global configuration registers. */
#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
@@ -35,17 +31,9 @@
#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
-static void it8712f_sio_write(u8 ldn, u8 index, u8 value)
-{
- outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
-}
-
-static void it8712f_enter_conf(void)
+static void pnp_enter_conf_state(device_t dev)
{
- u16 port = 0x2e; /* TODO: Don't hardcode! */
+ u16 port = dev >> 8;
outb(0x87, port);
outb(0x01, port);
@@ -53,17 +41,24 @@ static void it8712f_enter_conf(void)
outb((port == 0x4e) ? 0xaa : 0x55, port);
}
-static void it8712f_exit_conf(void)
+static void pnp_exit_conf_state(device_t dev)
{
- it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
+ pnp_set_logical_device(dev);
+ pnp_write_config(dev, IT8712F_CONFIG_REG_CC, 0x02);
}
/* Select 24MHz CLKIN (48MHz is the default). */
-void it8712f_24mhz_clkin(void)
+/*
+ * in romstage.c
+ * #define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+ * and pass: CLKIN_DEV
+ */
+void it8712f_24mhz_clkin(device_t dev)
{
- it8712f_enter_conf();
- it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1);
- it8712f_exit_conf();
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_write_config(dev, IT8712F_CONFIG_REG_CLOCKSEL, 0x01);
+ pnp_exit_conf_state(dev);
}
/*
@@ -75,43 +70,41 @@ void it8712f_24mhz_clkin(void)
* 0: 3VSBSW# will be always inactive.
* 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
*/
-void it8712f_enable_3vsbsw(void)
+/*
+ * in romstage.c
+ * #define VSBSW_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+ * and pass: VSBSW_DEV
+ */
+void it8712f_enable_3vsbsw(device_t dev)
{
- it8712f_enter_conf();
- it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80);
- it8712f_exit_conf();
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_write_config(dev, IT8712F_CONFIG_REG_MFC, 0x80);
+ pnp_exit_conf_state(dev);
}
-void it8712f_kill_watchdog(void)
+/*
+ * in romstage.c
+ * #define WDT_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+ * and pass: WTD_DEV
+ */
+void it8712f_kill_watchdog(device_t dev)
{
- it8712f_enter_conf();
- it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
- it8712f_exit_conf();
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_write_config(dev, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
+ pnp_exit_conf_state(dev);
}
/* Enable the serial port(s). */
void it8712f_enable_serial(device_t dev, u16 iobase)
{
- /* (1) Enter the configuration state (MB PnP mode). */
- it8712f_enter_conf();
-
- /* (2) Modify the data of configuration registers. */
-
- /*
- * Select the chip to configure (if there's more than one).
- * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
- * If this register is not written, both chips are configured.
- */
-
- /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
-
- /* Enable serial port(s). */
- it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */
- it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */
+ pnp_enter_conf_state(dev);
- /* Clear software suspend mode (clear bit 0). TODO: Needed? */
- /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
- /* (3) Exit the configuration state (MB PnP mode). */
- it8712f_exit_conf();
+ pnp_exit_conf_state(dev);
}
diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h
index 5ec6188..06d409d 100644
--- a/src/superio/ite/it8712f/it8712f.h
+++ b/src/superio/ite/it8712f/it8712f.h
@@ -35,8 +35,9 @@
#define IT8712F_GAME 0x09 /* GAME port */
#define IT8712F_IR 0x0a /* Consumer IR */
-void it8712f_kill_watchdog(void);
+void it8712f_kill_watchdog(device_t);
void it8712f_enable_serial(device_t dev, u16 iobase);
-void it8712f_24mhz_clkin(void);
-void it8712f_enable_3vsbsw(void);
-#endif
+void it8712f_24mhz_clkin(device_t);
+void it8712f_enable_3vsbsw(device_t);
+
+#endif /* SUPERIO_ITE_IT8712F_IT8712F_H */
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