[coreboot-gerrit] Patch set updated for coreboot: bbda56c AMD AGESA: Place CAR_GLOBAL in BSP stack

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Tue Sep 10 13:37:32 CEST 2013


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3832

-gerrit

commit bbda56c7be06f1cfd9806a3af6c2f9821703d3df
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Jul 29 10:16:14 2013 +0300

    AMD AGESA: Place CAR_GLOBAL in BSP stack
    
    Use BSP CPU's stack space to store CAR GLOBALS for the
    duration of romstage before CAR migration.
    
    NOTE: Such globals can only be accessed from BSP CPU due
    the way AMD platform has memory architecture set up.
    
    TODO: Add compile-time assertions to verify CAR configuration
    matches with the programming in vendorcode.
    
    Change-Id: Ica4700433268f484ce69a24d934732f9cfd4ba41
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/amd/agesa/Kconfig | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 142ba8e..9a3f174 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -51,6 +51,18 @@ config UDELAY_LAPIC_FIXED_FSB
 	int
 	default 200
 
+# TODO: Sync these with definitions in AGESA vendorcode.
+# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
+# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
+
+config DCACHE_RAM_BASE
+	hex
+	default 0x30000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x10000
+
 source src/cpu/amd/agesa/family10/Kconfig
 source src/cpu/amd/agesa/family12/Kconfig
 source src/cpu/amd/agesa/family14/Kconfig



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