[coreboot-gerrit] New patch to review for coreboot: 0e89bc3 timestamps intel: Move timestamp scratchpad to chipset
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sun Sep 8 12:13:19 CEST 2013
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3908
-gerrit
commit 0e89bc3663f48d48abe971077ae239ea7e87a1e2
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Sat Sep 7 11:38:56 2013 +0300
timestamps intel: Move timestamp scratchpad to chipset
This retrieves back the value stored with store_initial_timestamp()
in the bootblock for southbridge.
Change-Id: I377c823706c33ed65af023d20d2e4323edd31199
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/haswell/romstage.c | 5 +----
src/include/timestamp.h | 1 +
src/mainboard/google/butterfly/romstage.c | 5 +----
src/mainboard/google/link/romstage.c | 5 +----
src/mainboard/google/parrot/romstage.c | 5 +----
src/mainboard/google/stout/romstage.c | 5 +----
src/mainboard/intel/emeraldlake2/romstage.c | 5 +----
src/mainboard/kontron/ktqm77/romstage.c | 5 +----
src/mainboard/lenovo/t60/romstage.c | 5 +----
src/mainboard/lenovo/x60/romstage.c | 5 +----
src/mainboard/samsung/lumpy/romstage.c | 5 +----
src/mainboard/samsung/stumpy/romstage.c | 5 +----
src/southbridge/intel/bd82x6x/Makefile.inc | 2 +-
src/southbridge/intel/bd82x6x/early_pch.c | 33 +++++++++++++++++++++++++++++
src/southbridge/intel/i82801gx/Makefile.inc | 3 +--
src/southbridge/intel/i82801gx/early_lpc.c | 33 +++++++++++++++++++++++++++++
src/southbridge/intel/lynxpoint/early_pch.c | 12 +++++++++++
17 files changed, 92 insertions(+), 47 deletions(-)
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 0cef888..06e3a85 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -204,10 +204,7 @@ void romstage_common(const struct romstage_params *params)
tsc_t start_romstage_time;
tsc_t before_dram_time;
tsc_t after_dram_time;
- tsc_t base_time = {
- .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
- .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
- };
+ tsc_t base_time = get_initial_timestamp();
#endif
#if CONFIG_COLLECT_TIMESTAMPS
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index 9dd0d0f..2a39b97 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -61,6 +61,7 @@ void timestamp_add(enum timestamp_id id, tsc_t ts_time);
void timestamp_add_now(enum timestamp_id id);
void timestamp_stash(enum timestamp_id id);
void timestamp_sync(void);
+tsc_t get_initial_timestamp(void);
#else
#define timestamp_init(base)
#define timestamp_add(id, time)
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 5e2b713..554df83 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -122,10 +122,7 @@ void main(unsigned long bist)
tsc_t start_romstage_time;
tsc_t before_dram_time;
tsc_t after_dram_time;
- tsc_t base_time = {
- .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
- .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
- };
+ tsc_t base_time = get_initial_timestamp();
#endif
struct pei_data pei_data = {
pei_version: PEI_VERSION,
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index f20a722..ad4da84 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -158,10 +158,7 @@ void main(unsigned long bist)
tsc_t start_romstage_time;
tsc_t before_dram_time;
tsc_t after_dram_time;
- tsc_t base_time = {
- .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
- .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
- };
+ tsc_t base_time = get_initial_timestamp();
#endif
struct pei_data pei_data = {
pei_version: PEI_VERSION,
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 9968226..79f9c2a 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -123,10 +123,7 @@ void main(unsigned long bist)
tsc_t start_romstage_time;
tsc_t before_dram_time;
tsc_t after_dram_time;
- tsc_t base_time = {
- .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
- .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
- };
+ tsc_t base_time = get_initial_timestamp();
#endif
struct pei_data pei_data = {
pei_version: PEI_VERSION,
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 14820dd..80de53d 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -162,10 +162,7 @@ void main(unsigned long bist)
tsc_t start_romstage_time;
tsc_t before_dram_time;
tsc_t after_dram_time;
- tsc_t base_time = {
- .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
- .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
- };
+ tsc_t base_time = get_initial_timestamp();
#endif
struct pei_data pei_data = {
pei_version: PEI_VERSION,
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 88bcced..bb47cb8 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -174,10 +174,7 @@ void main(unsigned long bist)
tsc_t start_romstage_time;
tsc_t before_dram_time;
tsc_t after_dram_time;
- tsc_t base_time = {
- .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
- .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
- };
+ tsc_t base_time = get_initial_timestamp();
#endif
struct pei_data pei_data = {
pei_version: PEI_VERSION,
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 79fafe0..f78e293 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -160,10 +160,7 @@ void main(unsigned long bist)
tsc_t start_romstage_time;
tsc_t before_dram_time;
tsc_t after_dram_time;
- tsc_t base_time = {
- .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
- .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
- };
+ tsc_t base_time = get_initial_timestamp();
#endif
struct pei_data pei_data = {
pei_version: PEI_VERSION,
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 5bb7ac1..79a2988 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -216,10 +216,7 @@ void main(unsigned long bist)
tsc_t start_romstage_time;
tsc_t before_dram_time;
tsc_t after_dram_time;
- tsc_t base_time = {
- .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
- .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
- };
+ tsc_t base_time = get_initial_timestamp();
#endif
#if CONFIG_COLLECT_TIMESTAMPS
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 4d0eac7..ec4c00c 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -223,10 +223,7 @@ void main(unsigned long bist)
tsc_t start_romstage_time;
tsc_t before_dram_time;
tsc_t after_dram_time;
- tsc_t base_time = {
- .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
- .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
- };
+ tsc_t base_time = get_initial_timestamp();
#endif
#if CONFIG_COLLECT_TIMESTAMPS
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 449a81c..1a17949 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -141,10 +141,7 @@ void main(unsigned long bist)
tsc_t start_romstage_time;
tsc_t before_dram_time;
tsc_t after_dram_time;
- tsc_t base_time = {
- .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
- .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
- };
+ tsc_t base_time = get_initial_timestamp();
#endif
struct pei_data pei_data = {
pei_version: PEI_VERSION,
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index daa8d55..1169732 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -177,10 +177,7 @@ void main(unsigned long bist)
tsc_t start_romstage_time;
tsc_t before_dram_time;
tsc_t after_dram_time;
- tsc_t base_time = {
- .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
- .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
- };
+ tsc_t base_time = get_initial_timestamp();
#endif
struct pei_data pei_data = {
pei_version: PEI_VERSION,
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index ffd8943..8abc56a 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -47,7 +47,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c
romstage-y += reset.c
-romstage-y += early_spi.c
+romstage-y += early_spi.c early_pch.c
ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
new file mode 100644
index 0000000..9f80d41
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <timestamp.h>
+
+#if CONFIG_COLLECT_TIMESTAMPS
+tsc_t get_initial_timestamp(void)
+{
+ tsc_t base_time = {
+ .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+ .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+ };
+ return base_time;
+}
+#endif
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
index ff9fbee..94c84ed 100644
--- a/src/southbridge/intel/i82801gx/Makefile.inc
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -36,5 +36,4 @@ ramstage-y += watchdog.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-romstage-y += early_smbus.c
-
+romstage-y += early_smbus.c early_lpc.c
diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c
new file mode 100644
index 0000000..9f80d41
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/early_lpc.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <timestamp.h>
+
+#if CONFIG_COLLECT_TIMESTAMPS
+tsc_t get_initial_timestamp(void)
+{
+ tsc_t base_time = {
+ .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+ .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+ };
+ return base_time;
+}
+#endif
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index a390d73..1a78d57 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -21,6 +21,7 @@
#include <console/console.h>
#include <arch/io.h>
#include <device/pci_def.h>
+#include <timestamp.h>
#include <elog.h>
#include "pch.h"
@@ -62,6 +63,17 @@ static void pch_generic_setup(void)
printk(BIOS_DEBUG, " done.\n");
}
+#if CONFIG_COLLECT_TIMESTAMPS
+tsc_t get_initial_timestamp(void)
+{
+ tsc_t base_time = {
+ .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+ .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+ };
+ return base_time;
+}
+#endif
+
static int sleep_type_s3(void)
{
u32 pm1_cnt;
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