[coreboot-gerrit] Patch set updated for coreboot: 8429dff Store top_of_ram instead of cbmem_toc
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Sep 4 20:06:33 CEST 2013
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3557
-gerrit
commit 8429dffde5778b1ebb4df88165471b1dde63f052
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Wed Sep 4 13:26:11 2013 +0300
Store top_of_ram instead of cbmem_toc
Functions now backup and restore top_of_ram value.
Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/arch/x86/boot/ramtop.c | 6 ++++++
src/include/cbmem.h | 2 +-
src/lib/cbmem.c | 8 --------
src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++--
src/southbridge/amd/agesa/hudson/hudson.c | 9 ++++-----
src/southbridge/amd/cimx/sb700/lpc.c | 4 ++--
src/southbridge/amd/cimx/sb800/cfg.c | 8 ++++----
src/southbridge/amd/sb700/early_setup.c | 4 ++--
src/southbridge/amd/sb700/lpc.c | 4 ++--
src/southbridge/amd/sb800/early_setup.c | 4 ++--
src/southbridge/via/k8t890/early_car.c | 4 ++--
src/southbridge/via/k8t890/host_ctrl.c | 9 ++-------
src/southbridge/via/k8t890/k8t890.h | 2 +-
13 files changed, 30 insertions(+), 38 deletions(-)
diff --git a/src/arch/x86/boot/ramtop.c b/src/arch/x86/boot/ramtop.c
index fbd98a3..16faf48e 100644
--- a/src/arch/x86/boot/ramtop.c
+++ b/src/arch/x86/boot/ramtop.c
@@ -25,8 +25,14 @@ unsigned long __attribute__((weak)) get_top_of_ram(void)
}
#if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__)
+void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop)
+{
+ /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */
+}
+
void set_top_of_ram(uint64_t ramtop)
{
+ backup_top_of_ram(ramtop);
set_cbmem_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE);
}
#endif
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index f991168..87b7e9b 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -136,8 +136,8 @@ void cbmem_add_lb_mem(struct lb_memory *mem);
#ifndef __PRE_RAM__
extern uint64_t high_tables_base, high_tables_size;
void set_top_of_ram(uint64_t ramtop);
+void backup_top_of_ram(uint64_t ramtop);
void set_cbmem_table(uint64_t base, uint64_t size);
-void set_cbmem_toc(struct cbmem_entry *);
#endif
void cbmem_init(u64 baseaddr, u64 size);
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index bf32be0..27c1a27 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -49,10 +49,6 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
return bss_cbmem_toc;
}
-void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x)
-{
- /* do nothing, this should be called by chipset to save TOC in NVRAM */
-}
#else
struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
@@ -101,10 +97,6 @@ void cbmem_init(u64 baseaddr, u64 size)
for (;;) ;
}
- /* we don't need to call this in romstage, useful only from ramstage */
-#ifndef __PRE_RAM__
- set_cbmem_toc((struct cbmem_entry *)(unsigned long)baseaddr);
-#endif
memset(cbmem_toc, 0, CBMEM_TOC_RESERVED);
cbmem_toc[0] = (struct cbmem_entry) {
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index a0319ab..96861c9 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -95,7 +95,7 @@ int acpi_is_wakeup_early(void)
}
#endif
-struct cbmem_entry *get_cbmem_toc(void)
+unsigned long get_top_of_ram(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xf8, xi;
@@ -105,7 +105,7 @@ struct cbmem_entry *get_cbmem_toc(void)
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
- return (struct cbmem_entry *) xdata;
+ return (unsigned long) xdata;
}
#endif
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index e4cbc07..f78af1b 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -40,9 +40,9 @@ int acpi_get_sleep_type(void)
}
#endif
-void set_cbmem_toc(struct cbmem_entry *toc)
+void backup_top_of_ram(uint64_t ramtop)
{
- u32 dword = (u32) toc;
+ u32 dword = (u32) ramtop;
int nvram_pos = 0xf8, i; /* temp */
/* printk(BIOS_DEBUG, "dword=%x\n", dword); */
for (i = 0; i<4; i++) {
@@ -132,7 +132,7 @@ void hudson_enable(device_t dev)
}
}
-struct cbmem_entry *get_cbmem_toc(void)
+unsigned long get_top_of_ram(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xf8, xi;
@@ -142,10 +142,9 @@ struct cbmem_entry *get_cbmem_toc(void)
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
- return (struct cbmem_entry *) xdata;
+ return (unsigned long) xdata;
}
-
struct chip_operations southbridge_amd_agesa_hudson_ops = {
CHIP_NAME("ATI HUDSON")
.enable_dev = hudson_enable,
diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c
index 826ac05..91d7d2f 100644
--- a/src/southbridge/amd/cimx/sb700/lpc.c
+++ b/src/southbridge/amd/cimx/sb700/lpc.c
@@ -27,9 +27,9 @@
#define BIOSRAM_INDEX 0xcd4
#define BIOSRAM_DATA 0xcd5
-void set_cbmem_toc(struct cbmem_entry *toc)
+void backup_top_of_ram(uint64_t ramtop)
{
- u32 dword = (u32) toc;
+ u32 dword = (u32) ramtop;
int nvram_pos = 0xfc, i;
for (i = 0; i<4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 90ad5a9..0042974 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -37,9 +37,9 @@ int acpi_get_sleep_type(void)
#endif
#ifndef __PRE_RAM__
-void set_cbmem_toc(struct cbmem_entry *toc)
+void backup_top_of_ram(uint64_t ramtop)
{
- u32 dword = (u32) toc;
+ u32 dword = (u32) ramtop;
int nvram_pos = 0xf8, i; /* temp */
printk(BIOS_DEBUG, "dword=%x\n", dword);
for (i = 0; i<4; i++) {
@@ -51,7 +51,7 @@ void set_cbmem_toc(struct cbmem_entry *toc)
}
#endif
-struct cbmem_entry *get_cbmem_toc(void)
+unsigned long get_top_of_ram(void)
{
u32 xdata = 0;
int xnvram_pos = 0xf8, xi;
@@ -61,7 +61,7 @@ struct cbmem_entry *get_cbmem_toc(void)
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
- return (struct cbmem_entry *) xdata;
+ return (unsigned long) xdata;
}
/**
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index a16fc9f..f6612a2 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -731,7 +731,7 @@ int acpi_is_wakeup_early(void)
}
#endif
-struct cbmem_entry *get_cbmem_toc(void)
+unsigned long get_top_of_ram(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xfc, xi;
@@ -741,7 +741,7 @@ struct cbmem_entry *get_cbmem_toc(void)
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
- return (struct cbmem_entry *) xdata;
+ return (unsigned long) xdata;
}
#endif
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 23775b0..a175210 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -84,9 +84,9 @@ static void lpc_init(device_t dev)
rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
}
-void set_cbmem_toc(struct cbmem_entry *toc)
+void backup_top_of_ram(uint64_t ramtop)
{
- u32 dword = (u32) toc;
+ u32 dword = (u32) ramtop;
int nvram_pos = 0xfc, i;
for (i = 0; i<4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 4f0c98a..b860096 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -675,7 +675,7 @@ static int acpi_is_wakeup_early(void)
}
#endif
-struct cbmem_entry *get_cbmem_toc(void)
+unsigned long get_top_of_ram(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xfc, xi;
@@ -685,7 +685,7 @@ struct cbmem_entry *get_cbmem_toc(void)
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
- return (struct cbmem_entry *) xdata;
+ return (unsigned long) xdata;
}
#endif
diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c
index 000a532..8672801 100644
--- a/src/southbridge/via/k8t890/early_car.c
+++ b/src/southbridge/via/k8t890/early_car.c
@@ -183,6 +183,6 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
-struct cbmem_entry *get_cbmem_toc(void) {
- return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
+unsigned long get_top_of_ram(void) {
+ return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM);
}
diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c
index 151a228..74351bc 100644
--- a/src/southbridge/via/k8t890/host_ctrl.c
+++ b/src/southbridge/via/k8t890/host_ctrl.c
@@ -113,13 +113,8 @@ static void host_ctrl_enable_k8m8xx(struct device *dev) {
pci_write_config8(dev, 0xa6, 0x83);
}
-#if 0
-struct cbmem_entry *get_cbmem_toc(void) {
- return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
-}
-#endif
-void set_cbmem_toc(struct cbmem_entry *toc) {
- outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
+void backup_top_of_ram(uint64_t ramtop) {
+ outl((u32) ramtop, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM);
}
static struct pci_operations lops_pci = {
diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h
index f0d0fe0..7f83ffa 100644
--- a/src/southbridge/via/k8t890/k8t890.h
+++ b/src/southbridge/via/k8t890/k8t890.h
@@ -31,7 +31,7 @@
/* The 256 bytes of NVRAM for S3 storage, 256B aligned */
#define K8T890_NVRAM_IO_BASE 0xf00
-#define K8T890_NVRAM_CBMEM_TOC 0xfc
+#define K8T890_NVRAM_TOP_OF_RAM 0xfc
#define K8T890_MMCONFIG_MBAR 0x61
#define K8T890_MULTIPLE_FN_EN 0x4f
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