[coreboot-gerrit] Patch set updated for coreboot: 6ee575c dmp/vortex86ex: Initialize I2C controller base address/IRQ

Andrew Wu (arw@dmp.com.tw) gerrit at coreboot.org
Sat Oct 19 10:04:43 CEST 2013


Andrew Wu (arw at dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3976

-gerrit

commit 6ee575c51ec32dcd1df7dc1783f55148cb310d51
Author: Andrew Wu <arw at dmp.com.tw>
Date:   Wed Oct 16 13:08:30 2013 +0800

    dmp/vortex86ex: Initialize I2C controller base address/IRQ
    
    Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce
    Signed-off-by: Andrew Wu <arw at dmp.com.tw>
---
 src/mainboard/dmp/vortex86ex/platform_cfg.h  | 31 ++++++++++++++++++++++++++++
 src/southbridge/dmp/vortex86ex/southbridge.c | 12 +++++++++++
 src/southbridge/dmp/vortex86ex/southbridge.h |  1 +
 3 files changed, 44 insertions(+)

diff --git a/src/mainboard/dmp/vortex86ex/platform_cfg.h b/src/mainboard/dmp/vortex86ex/platform_cfg.h
new file mode 100644
index 0000000..61adf57
--- /dev/null
+++ b/src/mainboard/dmp/vortex86ex/platform_cfg.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PLATFORM_CFG_H_
+#define _PLATFORM_CFG_H_
+
+/* In-chip PCI device IRQs(0 for disabled). */
+/* Internal I2C */
+#define I2C0_IRQ 10
+
+/* In-chip device I/O base address. */
+/* Internal I2C */
+#define I2C_BASE 0xfb00
+
+#endif
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c
index d8914c0..675cf49 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.c
+++ b/src/southbridge/dmp/vortex86ex/southbridge.c
@@ -28,6 +28,7 @@
 #include "arch/io.h"
 #include "chip.h"
 #include "southbridge.h"
+#include "mainboard/dmp/vortex86ex/platform_cfg.h"
 
 /* IRQ number to S/B PCI Interrupt routing table reg(0x58/0xb4) mapping table. */
 static const unsigned char irq_to_int_routing[16] = {
@@ -418,6 +419,16 @@ static void ex_sb_uart_init(struct device *dev)
 	//pci_write_config16(SB, SB_REG_UART_CFG_IO_BASE, 0x0);
 }
 
+static void i2c_init(struct device *dev)
+{
+	u8 mapped_irq = irq_to_int_routing[I2C0_IRQ];
+	u32 cfg = 0;
+	cfg |= 1 << 31;			// UE = enabled.
+	cfg |= (mapped_irq << 16);	// IIRT0.
+	cfg |= I2C_BASE;		// UIOA.
+	pci_write_config32(dev, SB_REG_II2CCR, cfg);
+}
+
 static int get_rtc_update_in_progress(void)
 {
 	if (cmos_read(RTC_REG_A) & RTC_UIP)
@@ -566,6 +577,7 @@ static void southbridge_init(struct device *dev)
 	if (dev->device == 0x6011) {
 		ex_sb_gpio_init(dev);
 		ex_sb_uart_init(dev);
+		i2c_init(dev);
 	}
 	pci_routing_fixup(dev);
 
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.h b/src/southbridge/dmp/vortex86ex/southbridge.h
index 0cc28fa..316d30a 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.h
+++ b/src/southbridge/dmp/vortex86ex/southbridge.h
@@ -36,6 +36,7 @@
 #define	SB_REG_IPFCR		0xc0
 #define	SB_REG_FRWPR		0xc4
 #define	SB_REG_STRAP		0xce
+#define	SB_REG_II2CCR		0xd4
 
 #define	SB1			PCI_DEV(0, 7, 1)
 #define	SB1_REG_EXT_PIRQ_ROUTE2	0xb4



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