[coreboot-gerrit] Patch set updated for coreboot: f833ff7 ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1

Jonathan A. Kollasch (jakllsch@kollasch.net) gerrit at coreboot.org
Sun Oct 13 18:55:50 CEST 2013


Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3963

-gerrit

commit f833ff7b2ddaf6dbbd046709a38eaaa3aca2772b
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Fri Oct 11 16:14:18 2013 -0500

    ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1
    
    Linux unhelpfully "fixes" the value in PCI_BASE_ADDRESS_1 when it is
    0xfec00000 (that is, outside the range of bus 0 address space).  This
    causes IOAPIC interrupts to fail to work under Linux.  This issue was
    originally unnoticed by me when testing as sanity checking such as
    this is not done by NetBSD.
    
    Hiding the IOAPIC BAR is done by the OEM BIOS on the ck804 boards I've
    checked.
    
    Change-Id: I736db163750f709d68c988fac075597a50b29ab7
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
---
 src/southbridge/nvidia/ck804/lpc.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index 4b33a3c..b3a9b00 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -53,15 +53,10 @@
 
 static void lpc_common_init(device_t dev)
 {
-	u8 byte;
 	u32 dword;
 	struct resource *res;
 
 	/* I/O APIC initialization. */
-	byte = pci_read_config8(dev, 0x74);
-	byte |= (1 << 0);	/* Enable APIC. */
-	pci_write_config8(dev, 0x74, byte);
-
 	res = find_resource(dev, PCI_BASE_ADDRESS_1);  /* IOAPIC */
 	ASSERT(res != NULL);
 	setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */
@@ -221,6 +216,7 @@ static void ck804_lpc_read_resources(device_t dev)
 
 static void ck804_lpc_set_resources(device_t dev)
 {
+	u8 byte;
 	struct resource *res;
 
 	pci_dev_set_resources(dev);
@@ -228,9 +224,15 @@ static void ck804_lpc_set_resources(device_t dev)
 	/* APIC */
 	res = find_resource(dev, PCI_BASE_ADDRESS_1);
 	if (res) {
+		byte = pci_read_config8(dev, 0x74);
+		byte |= (1 << 1);	/* enable access to PCI_BASE_ADDRESS_1 */
+		pci_write_config8(dev, 0x74, byte);
 		pci_write_config32(dev, PCI_BASE_ADDRESS_1, res->base);
 		res->flags |= IORESOURCE_STORED;
 		report_resource_stored(dev, res, "");
+		byte |= (1 << 0);	/* enable decode of IOAPIC space */
+		byte &= ~(1 << 1);	/* hide PCI_BASE_ADDRESS_1 */
+		pci_write_config8(dev, 0x74, byte);
 	}
 
 	/* HPET */



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