[coreboot-gerrit] Patch set updated for coreboot: 380cf8f ck804: obtain stored IOAPIC address from allocator instead of register

[Jonathan A. Kollasch (jakllsch@kollasch.net)]

Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3961

-gerrit

commit 380cf8f666a0408c40b7014b4691be1a2d5e166e
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Fri Oct 11 15:52:30 2013 -0500

    ck804: obtain stored IOAPIC address from allocator instead of register
    
    Change-Id: Ibdd438455a545aa9266b0fd893d5ff27124ab22c
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
---
 src/southbridge/nvidia/ck804/lpc.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index 1f49000..c3f24bc 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -32,6 +32,7 @@
 #include <arch/ioapic.h>
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
+#include <assert.h>
 #include "ck804.h"
 
 #define CK804_CHIP_REV 2
@@ -54,14 +55,16 @@ static void lpc_common_init(device_t dev)
 {
 	u8 byte;
 	u32 dword;
+	struct resource *res;
 
 	/* I/O APIC initialization. */
 	byte = pci_read_config8(dev, 0x74);
 	byte |= (1 << 0);	/* Enable APIC. */
 	pci_write_config8(dev, 0x74, byte);
-	dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1);	/* 0x14 */
 
-	setup_ioapic(dword, 0); /* Don't rename IOAPIC ID. */
+	res = find_resource(dev, PCI_BASE_ADDRESS_1);  /* IOAPIC */
+	ASSERT(res != NULL);
+	setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */
 
 #if 1
 	dword = pci_read_config32(dev, 0xe4);