[coreboot-gerrit] New patch to review for coreboot: 2a8b2eb dmp/vortex86ex: Initialize PS/2 keyboard.

[Andrew Wu (arw@dmp.com.tw)]

Andrew Wu (arw at dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3957

-gerrit

commit 2a8b2eb3c5ed6c184af175c807f062a8002d3ccb
Author: Andrew Wu <arw at dmp.com.tw>
Date:   Wed Oct 9 18:57:20 2013 +0800

    dmp/vortex86ex: Initialize PS/2 keyboard.
    
    Call pc_keyboard_init function in southbridge. It makes PS/2
    keyboard work in coreinfo payload.
    
    Change-Id: Idb79f87b09eeeade94e966fb8769dec7578e2cf5
    Signed-off-by: Andrew Wu <arw at dmp.com.tw>
---
 src/southbridge/dmp/vortex86ex/southbridge.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c
index a22fe6a..d2e9626 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.c
+++ b/src/southbridge/dmp/vortex86ex/southbridge.c
@@ -23,6 +23,7 @@
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <pc80/mc146818rtc.h>
+#include <pc80/keyboard.h>
 #include <string.h>
 #include "arch/io.h"
 #include "chip.h"
@@ -137,6 +138,10 @@ static void upload_dmp_keyboard_firmware(struct device *dev)
 
 	// disable firmware uploading.
 	pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 & ~0x400L);
+}
+
+static void wait_dmp_keyboard_firmware_ready(void)
+{
 	// wait keyboard controller ready by checking status port bit 2.
 	post_code(POST_KBD_CHK_READY);
 	while ((inb(0x64) & 0x4) == 0) {
@@ -570,6 +575,8 @@ static void southbridge_init(struct device *dev)
 
 	fix_cmos_rtc_time();
 	rtc_init(0);
+	wait_dmp_keyboard_firmware_ready();
+	pc_keyboard_init(0);
 }
 
 static struct device_operations vortex_sb_ops = {