[coreboot-gerrit] Patch merged into coreboot/master: 98c4062 lynxpoint: Enable SerialIO clock in PCI mode
gerrit at coreboot.org
gerrit at coreboot.org
Mon Nov 25 23:36:58 CET 2013
the following patch was just integrated into master:
commit 98c40622feeaf1d8f211501e8f337d5bde544d13
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Tue May 21 16:37:40 2013 -0700
lynxpoint: Enable SerialIO clock in PCI mode
The clock gating register at offset 0x800 is managed by the
clock driver in the kernel when the devices are in ACPI mode.
When in PCI mode we should force enable the clock here.
When in ACPI mode or the device is disabled it should be put
in D3Hot state.
> i2cdetect -y -r 10
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: -- -- -- -- -- -- -- -- -- -- -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- --
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- --
Change-Id: Ib93ffd41bf36386d5ce63bfc0ae6597f3e23bc48
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56122
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: http://review.coreboot.org/4180
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>
See http://review.coreboot.org/4180 for details.
-gerrit
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