[coreboot-gerrit] Patch merged into coreboot/master: 441a4ba libpayload (EHCI): correctly align PORTSC

gerrit at coreboot.org gerrit at coreboot.org
Mon Nov 25 23:31:36 CET 2013

the following patch was just integrated into master:
commit 441a4baf87ada2608a109a203a5d8040f6dc2b0d
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri May 17 11:56:09 2013 -0700

    libpayload (EHCI): correctly align PORTSC
    Two structures in the USB EHCI stack were pointing
    to hardware but not marked attribute((packed)) hence
    leaving it to GCC to correctly align the data structures.
    Next, the number of reserved bytes in hc_op_t was wrong
    (but implicitly aligned to the correct values on x86)
    It seems this worked fine on x86, but on ARM it was doing
    the wrong thing.
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    Change-Id: I94bed4850ded7d3f7bbc7ff3079c103c6054c22d
    Reviewed-on: https://gerrit.chromium.org/gerrit/55555
    Commit-Queue: Stefan Reinauer <reinauer at google.com>
    Reviewed-by: Stefan Reinauer <reinauer at google.com>
    Tested-by: Stefan Reinauer <reinauer at google.com>
    Reviewed-on: http://review.coreboot.org/4174
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

See http://review.coreboot.org/4174 for details.


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