[coreboot-gerrit] Patch merged into coreboot/master: 7c35131 haswell: configure c-states
gerrit at coreboot.org
gerrit at coreboot.org
Sun Nov 24 16:01:40 CET 2013
the following patch was just integrated into master:
commit 7c351316429f8b991df7ea233a5528f4efb3b8e0
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Apr 10 14:46:25 2013 -0500
haswell: configure c-states
The c-states are configured according to the BWG, however the
package c-states are disabled as they currently cause platform
instability. The exposed ACPI c-state to processor c-state mapping
are as follows for ULT boards:
ACPI(C1) = MWAIT(C1E)
ACPI(C2) = MWAIT(C7S long latency)
ACPI(C3) = MWAIT(C10)
The non-ULT boards have an expoed c-state mapping:
ACPI(C1) = MWAIT(C1E)
ACPI(C2) = MWAIT(C3)
ACPI(C3) = MWAIT(C7S)
Included in this patch is removing the updating of current limit
registers as some of the MSRs are different and the proper values
are currently unknown. Lastly, some of the MSRs were renamed to
match the BWG.
Booted 3.8 kernel and used powertop to note package, core, and acpi
c-state residency.
Change-Id: Ia428d4a4979ba3cba44eb9faa96f74b7d3f22dfe
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48291
Commit-Queue: Stefan Reinauer <reinauer at google.com>
Tested-by: Stefan Reinauer <reinauer at google.com>
Reviewed-on: http://review.coreboot.org/4133
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
See http://review.coreboot.org/4133 for details.
-gerrit
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