[coreboot-gerrit] Patch merged into coreboot/master: 25b8b7b haswell: Put each logical processor in its own P-state domain

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 25b8b7b8813f849c132db597510c4d61c47566fa
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Apr 19 10:02:23 2013 -0700

    haswell: Put each logical processor in its own P-state domain
    
    The recommendation from Intel is to report each core as a
    separate logical domain in the _PSD table.
    
    This goes against the recommendation in the ACPI specification
    because all of these cores are on the same package and share a
    VR so they will do voltage transitions together.
    
    The reasoning is that with a larger number of logical processors
    the P-state often ramps too quickly resulting in higher power
    consumption.  By exposing each core as a separate domain the OS
    can manage them individually allowing the socket to select the
    optimum frequency.
    
    $ cat /sys/firmware/acpi/tables/SSDT > /tmp/SSDT
    $ iasl -d /tmp/SSDT
    
    Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00)
    {
      Name (_PSD, Package (0x01)
      {
        Package (0x05)
        {
          0x05,
          0x00,
          0x00000000,
          0x000000FE,
          0x00000001
        }
      })
    }
    
    Processor (\_PR.CPU1, 0x01, 0x00000000, 0x00)
    {
      Name (_PSD, Package (0x01)
      {
        Package (0x05)
        {
          0x05,
          0x00,
          0x00000001,
          0x000000FE,
          0x00000001
        }
      })
    }
    
    Processor (\_PR.CPU2, 0x02, 0x00000000, 0x00)
    {
      Name (_PSD, Package (0x01)
      {
        Package (0x05)
        {
          0x05,
          0x00,
          0x00000002,
          0x000000FE,
          0x00000001
        }
      })
    }
    
    Processor (\_PR.CPU3, 0x03, 0x00000000, 0x00)
    {
      Name (_PSD, Package (0x01)
      {
        Package (0x05)
        {
          0x05,
          0x00,
          0x00000003,
          0x000000FE,
          0x00000001
        }
      })
    }
    
    Change-Id: I5ef41b6ead4d88e9ba117003293dbc629c376803
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48662
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/4130
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>


See http://review.coreboot.org/4130 for details.

-gerrit