[coreboot-gerrit] Patch set updated for coreboot: 1b52094 wtm2: Set SerialIO I2C ports to 3.3V
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Wed Nov 20 01:51:15 CET 2013
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4164
-gerrit
commit 1b5209481e862e599030c29709c991ec0929d467
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Tue May 7 13:28:56 2013 -0700
wtm2: Set SerialIO I2C ports to 3.3V
These are both pulled up to 3.3V in the schematic.
Change-Id: I12e055a39ff6100300c3d285899b8d6239e3773d
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50356
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/intel/wtm2/devicetree.cb | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb
index 3193369..2790cb9 100644
--- a/src/mainboard/intel/wtm2/devicetree.cb
+++ b/src/mainboard/intel/wtm2/devicetree.cb
@@ -52,8 +52,8 @@ chip northbridge/intel/haswell
register "sata_port_map" = "0x2"
register "sio_acpi_mode" = "1"
- register "sio_i2c0_voltage" = "1" # 1.8V
- register "sio_i2c1_voltage" = "1" # 1.8V
+ register "sio_i2c0_voltage" = "0" # 3.3V
+ register "sio_i2c1_voltage" = "0" # 3.3V
device pci 13.0 on end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
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