[coreboot-gerrit] Patch set updated for coreboot: 0f327c9 haswell: calibrate 24MHz clock against BCLK

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4136

-gerrit

commit 0f327c9f3b566470d6d7d2ce80c9da65472303d5
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Apr 10 14:59:21 2013 -0500

    haswell: calibrate 24MHz clock against BCLK
    
    On haswell ULT systems there is a 24MHz clock that continuously runs
    when deep package c-states are entered. The 100MHz BCLK is shut down
    in the lower c-states. When the package wakes back up a conversion
    formula needs to be applied. The 24MHz calibration is done using the
    internal PCODE unit.
    
    Change-Id: I6be7702fb1de1429273724536f5af9125b98da64
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48292
    Tested-by: Stefan Reinauer <reinauer at google.com>
    Commit-Queue: Stefan Reinauer <reinauer at google.com>
---
 src/cpu/intel/haswell/haswell.h      | 19 ++++++++++++
 src/cpu/intel/haswell/haswell_init.c | 60 ++++++++++++++++++++++++++++++++++++
 2 files changed, 79 insertions(+)

diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index ab1cef4..96f94eb 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -100,6 +100,25 @@
 #define PSS_LATENCY_TRANSITION		10
 #define PSS_LATENCY_BUSMASTER		10
 
+/* PCODE MMIO communications live in the MCHBAR. */
+#define BIOS_MAILBOX_INTERFACE			0x5da4
+#define  MAILBOX_RUN_BUSY			(1 << 31)
+#define  MAILBOX_BIOS_CMD_READ_PCS		1
+#define  MAILBOX_BIOS_CMD_WRITE_PCS		2
+#define  MAILBOX_BIOS_CMD_READ_CALIBRATION	0x509
+#define  MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL	0x909
+/* Errors are returned back in bits 7:0. */
+#define  MAILBOX_BIOS_ERROR_NONE		0
+#define  MAILBOX_BIOS_ERROR_INVALID_COMMAND	1
+#define  MAILBOX_BIOS_ERROR_TIMEOUT		2
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_DATA	3
+#define  MAILBOX_BIOS_ERROR_RESERVED		4
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID	5
+#define  MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED	6
+#define  MAILBOX_BIOS_ERROR_VR_ERROR		7
+/* Data is passed through bits 31:0 of the data register. */
+#define BIOS_MAILBOX_DATA			0x5da0
+
 /* Region of SMM space is reserved for multipurpose use. It falls below
  * the IED region and above the SMM handler. */
 #define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 5b53afe..0b7a898 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -34,6 +34,7 @@
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
+#include <delay.h>
 #include <pc80/mc146818rtc.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <southbridge/intel/lynxpoint/pch.h>
@@ -217,6 +218,62 @@ static int is_ult(void)
 	return ult;
 }
 
+/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
+ * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
+ * when a core is woken up. */
+static int pcode_ready(void)
+{
+	int wait_count;
+	const int delay_step = 10;
+
+	wait_count = 0;
+	do {
+		if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY))
+			return 0;
+		wait_count += delay_step;
+		udelay(delay_step);
+	} while (wait_count < 1000);
+
+	return -1;
+}
+
+static void calibrate_24mhz_bclk(void)
+{
+	int err_code;
+
+	if (pcode_ready() < 0) {
+		printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n");
+		return;
+	}
+
+	/* A non-zero value initiates the PCODE calibration. */
+	MCHBAR32(BIOS_MAILBOX_DATA) = ~0;
+	MCHBAR32(BIOS_MAILBOX_INTERFACE) =
+		MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL;
+
+	if (pcode_ready() < 0) {
+		printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n");
+		return;
+	}
+
+	err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff;
+
+	printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n",
+	       err_code);
+
+	/* Read the calibrated value. */
+	MCHBAR32(BIOS_MAILBOX_INTERFACE) =
+		MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION;
+
+	if (pcode_ready() < 0) {
+		printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n",
+	       MCHBAR32(BIOS_MAILBOX_DATA));
+}
+
 int cpu_config_tdp_levels(void)
 {
 	msr_t platform_info;
@@ -517,6 +574,9 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus)
 	x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2);
 	x86_mtrr_check();
 
+	if (is_ult())
+		calibrate_24mhz_bclk();
+
 	/* Call through the cpu driver's initialization. */
 	cpu_initialize(0);
 }