[coreboot-gerrit] New patch to review for coreboot: 2b350a1 slippy: Prepare LPC IO decode ranges for EC

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Tue Nov 19 00:44:06 CET 2013


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4151

-gerrit

commit 2b350a1b399467e87650514ff3ba580f34949c7c
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed May 1 11:12:53 2013 -0700

    slippy: Prepare LPC IO decode ranges for EC
    
    - 0x200-0x208 for host command window
    - 0x800-0x8ff for host command arguments and parameters
    - 0x900-0x9ff for exported EC memory map
    
    Change-Id: I064b969843ef0d3c602793d1cb3d82715775c05e
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49755
---
 src/mainboard/google/slippy/devicetree.cb   | 4 ++++
 src/southbridge/intel/lynxpoint/early_pch.c | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index 8cf387f..5fb3cb4 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -41,6 +41,10 @@ chip northbridge/intel/haswell
 			register "pirqg_routing" = "0x80"
 			register "pirqh_routing" = "0x80"
 
+			# EC range is 0x800-0x9ff
+			register "gen1_dec" = "0x00fc0801"
+			register "gen2_dec" = "0x00fc0901"
+
 			register "alt_gp_smi_en" = "0x0000"
 			register "gpe0_en_1" = "0x00000000"
 			# EC_SCI is GPIO36
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 1a78d57..7a24e1f 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -102,7 +102,7 @@ static void pch_enable_lpc(void)
 	pci_write_config16(dev, LPC_IO_DEC, 0x0010);
 
 	/* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */
-	u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN |
+	u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
 		COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
 	pci_write_config16(dev, LPC_EN, lpc_config);
 }



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