[coreboot-gerrit] Patch set updated for coreboot: 8edc447 intel/2065x: Use TSC for udelay()

[Vladimir Serbinenko (phcoder@gmail.com)]

Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4043

-gerrit

commit 8edc4473487357698c0889f85ba60e21069bc666
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Tue Nov 12 21:59:10 2013 +0100

    intel/2065x: Use TSC for udelay()
    
    For the ram init of Intel Nehalem ram init we need a udelay implementation.
    Use common TSC framework for it as Intel Haswell already does.
    
    Change-Id: I360a6db1ec1ba32c92698a7d6f6968c93ead5c52
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
 src/cpu/intel/model_2065x/Kconfig      |  3 ++-
 src/cpu/intel/model_2065x/Makefile.inc |  6 ++++++
 src/cpu/intel/model_2065x/tsc_freq.c   | 31 +++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index 019309d..b0f4e65 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS
 	select SMP
 	select SSE
 	select SSE2
-	select UDELAY_LAPIC
+	select UDELAY_TSC
+	select TSC_CONSTANT_RATE
 	select SMM_TSEG
 	select HAVE_INIT_TIMER
 	select CPU_MICROCODE_IN_CBFS
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 963fb1b..3b3fc4e 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -3,10 +3,16 @@ subdirs-y += ../../x86/name
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/tsc
 subdirs-y += ../../intel/turbo
 subdirs-y += ../../intel/microcode
 subdirs-y += ../../x86/smm
 
+
+ramstage-y += tsc_freq.c
+romstage-y += tsc_freq.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
+
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
diff --git a/src/cpu/intel/model_2065x/tsc_freq.c b/src/cpu/intel/model_2065x/tsc_freq.c
new file mode 100644
index 0000000..7d388be
--- /dev/null
+++ b/src/cpu/intel/model_2065x/tsc_freq.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include "model_2065x.h"
+
+unsigned long tsc_freq_mhz(void)
+{
+	msr_t platform_info;
+
+	platform_info = rdmsr(MSR_PLATFORM_INFO);
+	return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff);
+}