[coreboot-gerrit] New patch to review for coreboot: bc1aa41 emeraldlake2: Clean up COM port enable
Marc Jones (marc.jones@se-eng.com)
gerrit at coreboot.org
Wed Nov 6 06:10:52 CET 2013
Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4027
-gerrit
commit bc1aa412f6649262d9bfb964f26cba0b86b49478
Author: Marc Jones <marc.jones at se-eng.com>
Date: Tue Nov 5 17:47:37 2013 -0700
emeraldlake2: Clean up COM port enable
Remove the COM port enable loop. It doesn't make sense as the
COMA was enabled a few lines above the loop.
Change-Id: Ie4e533fd9e49ed9ae62b209317b4b9853ff9926a
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
src/mainboard/intel/emeraldlake2/romstage.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 7691116..32e1c11 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -45,7 +45,6 @@
static void pch_enable_lpc(void)
{
device_t dev = PCH_LPC_DEV;
- int i;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
@@ -57,17 +56,8 @@ static void pch_enable_lpc(void)
/* Map 256 bytes at 0x1600 to the LPC bus. */
pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601);
- /* Map a range for the runtime registers to the LPC bus. */
+ /* Map a range for the runtime_port registers to the LPC bus. */
pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181);
-
- for (i = 0; i < ARRAY_SIZE(sio1007_lpc_ports); i++) {
- if (sio1007_enable_uart_at(sio1007_lpc_ports[i])) {
- /* Keep COMA UART enable bit on. */
- pci_write_config16(dev, LPC_EN,
- lpc_config | COMA_LPC_EN);
- break;
- }
- }
}
static void rcba_config(void)
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