[coreboot-gerrit] Patch set updated for coreboot: af4fd6b SPI controller base address gets overwritten by SD controller under Linux

[Steven Sherk (steven.sherk@se-eng.com)]

Steven Sherk (steven.sherk at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3270

-gerrit

commit af4fd6b823778528b6e0cd5e4d3caf1fd742ee8e
Author: Steven Sherk <steven.sherk at se-eng.com>
Date:   Wed May 22 13:49:18 2013 -0600

    SPI controller base address gets overwritten by SD controller under Linux
    
        - Reason for overwrite is the spi base address isn't in a standard BAR and doesn't
          get automatically reserved. Solution is to add it as a reserved memory area in
          ACPI.
    
        - This issue was found on the ASUS F2a85-m platform. Currently a workaround on this
          platform was made as part of: http://review.coreboot.org/#/c/3167/3
    
        - Once approved a follow-on patch for other southbridges using a non-standard BAR for
          the spi controller.
    
    Change-Id: I1b67da3045729a6754e245141cd83c5b3cc9009e
    Signed-off-by: Steven Sherk <steven.sherk at se-eng.com>
---
 src/mainboard/amd/parmer/dsdt.asl   | 27 +++++++++++++++++++++++++++
 src/mainboard/amd/thatcher/dsdt.asl | 27 +++++++++++++++++++++++++++
 src/mainboard/asus/f2a85-m/dsdt.asl | 27 +++++++++++++++++++++++++++
 3 files changed, 81 insertions(+)

diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl
index faf3ad7..8b879ae 100644
--- a/src/mainboard/amd/parmer/dsdt.asl
+++ b/src/mainboard/amd/parmer/dsdt.asl
@@ -1242,6 +1242,33 @@ DefinitionBlock (
 				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
 				} */ /* End Method(_SB.SBRDG._INI) */
 
+			    OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
+				Field(CFG,DWordAcc,NoLock,Preserve){
+				Offset(0xA0),
+				BAR,32}		// SPI Controller Base Address Register (Index 0xA0)
+
+				Device(LDRC)	// LPC device: Resource consumption
+				{
+						Name (_HID, EISAID("PNP0C02"))  // ID for Motherboard resources
+						Name (CRS, ResourceTemplate ()  // Current Motherboard resources
+						{
+							Memory32Fixed(ReadWrite,    // Setup for fixed resource location for SPI base address
+							0x00000000,					// Address Base
+							0x00000000,					// Address Length
+							BAR0						// Descriptor Name
+							)
+						})
+
+						Method(_CRS,0,NotSerialized)
+						{
+							CreateDwordField(^CRS,^BAR0._BAS,SPIB)  // Field to hold SPI base address
+							CreateDwordField(^CRS,^BAR0._LEN,SPIL)  // Field to hold SPI address length
+							Store(BAR,SPIB)		// SPI base address mapped
+							Store(0x1000,SPIL)	// 4k space mapped
+							Return(CRS)
+						}
+				}
+
 				/* Real Time Clock Device */
 				Device(RTC0) {
 					Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl
index faf3ad7..7f08bbb 100644
--- a/src/mainboard/amd/thatcher/dsdt.asl
+++ b/src/mainboard/amd/thatcher/dsdt.asl
@@ -1242,6 +1242,33 @@ DefinitionBlock (
 				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
 				} */ /* End Method(_SB.SBRDG._INI) */
 
+				OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
+				Field(CFG,DWordAcc,NoLock,Preserve){
+				Offset(0xA0),
+				BAR,32}		// SPI Controller Base Address Register (Index 0xA0)
+
+				Device(LDRC)	// LPC device: Resource consumption
+				{
+						Name (_HID, EISAID("PNP0C02"))  // ID for Motherboard resources
+						Name (CRS, ResourceTemplate ()  // Current Motherboard resources
+						{
+							Memory32Fixed(ReadWrite,    // Setup for fixed resource location for SPI base address
+							0x00000000,					// Address Base
+							0x00000000,					// Address Length
+							BAR0						// Descriptor Name
+							)
+						})
+
+						Method(_CRS,0,NotSerialized)
+						{
+							CreateDwordField(^CRS,^BAR0._BAS,SPIB)  // Field to hold SPI base address
+							CreateDwordField(^CRS,^BAR0._LEN,SPIL)  // Field to hold SPI address length
+							Store(BAR,SPIB)		// SPI base address mapped
+							Store(0x1000,SPIL)	// 4k space mapped
+							Return(CRS)
+						}
+				}
+
 				/* Real Time Clock Device */
 				Device(RTC0) {
 					Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl
index d9f8fa4..dc0fdaa 100644
--- a/src/mainboard/asus/f2a85-m/dsdt.asl
+++ b/src/mainboard/asus/f2a85-m/dsdt.asl
@@ -1235,6 +1235,33 @@ DefinitionBlock (
 				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
 				} */ /* End Method(_SB.SBRDG._INI) */
 
+				OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
+				Field(CFG,DWordAcc,NoLock,Preserve){
+				Offset(0xA0),
+				BAR,32}		// SPI Controller Base Address Register (Index 0xA0)
+
+				Device(LDRC)	// LPC device: Resource consumption
+				{
+						Name (_HID, EISAID("PNP0C02"))  // ID for Motherboard resources
+						Name (CRS, ResourceTemplate ()  // Current Motherboard resources
+						{
+							Memory32Fixed(ReadWrite,    // Setup for fixed resource location for SPI base address
+							0x00000000,					// Address Base
+							0x00000000,					// Address Length
+							BAR0						// Descriptor Name
+							)
+						})
+
+						Method(_CRS,0,NotSerialized)
+						{
+							CreateDwordField(^CRS,^BAR0._BAS,SPIB)  // Field to hold SPI base address
+							CreateDwordField(^CRS,^BAR0._LEN,SPIL)  // Field to hold SPI address length
+							Store(BAR,SPIB)		// SPI base address mapped
+							Store(0x1000,SPIL)	// 4k space mapped
+							Return(CRS)
+						}
+				}
+
 				/* Real Time Clock Device */
 				Device(RTC0) {
 					Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */