[coreboot-gerrit] Patch merged into coreboot/master: 393619b intel/gm45: Add more debug output to read/write training

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 393619b9a6dc1db73421f9c731feaa9201d85e61
Author: Nico Huber <nico.huber at secunet.com>
Date:   Tue May 14 12:28:42 2013 +0200

    intel/gm45: Add more debug output to read/write training
    
    Add debug output for the timing values of the edges found during
    read and write training.
    
    Now, output for one DIMM of DDR3-1066 in a roda/rk9 looks like:
    
    [...]
    Lower bound for byte lane 0 on channel 0: 0.0
    Upper bound for byte lane 0 on channel 0: 8.4
    Final timings for byte lane 0 on channel 0: 4.2
    Lower bound for byte lane 1 on channel 0: 0.0
    Upper bound for byte lane 1 on channel 0: 10.2
    Final timings for byte lane 1 on channel 0: 5.1
    Lower bound for byte lane 2 on channel 0: 0.0
    Upper bound for byte lane 2 on channel 0: 7.5
    Final timings for byte lane 2 on channel 0: 3.6
    Lower bound for byte lane 3 on channel 0: 0.0
    Upper bound for byte lane 3 on channel 0: 11.4
    Final timings for byte lane 3 on channel 0: 5.6
    Lower bound for byte lane 4 on channel 0: 0.0
    Upper bound for byte lane 4 on channel 0: 9.4
    Final timings for byte lane 4 on channel 0: 4.6
    Lower bound for byte lane 5 on channel 0: 0.0
    Upper bound for byte lane 5 on channel 0: 11.2
    Final timings for byte lane 5 on channel 0: 5.5
    Lower bound for byte lane 6 on channel 0: 0.0
    Upper bound for byte lane 6 on channel 0: 8.4
    Final timings for byte lane 6 on channel 0: 4.2
    Lower bound for byte lane 7 on channel 0: 0.0
    Upper bound for byte lane 7 on channel 0: 10.4
    Final timings for byte lane 7 on channel 0: 5.2
    Lower bound for group 0 on channel 0: 1.7.5
    Upper bound for group 0 on channel 0: 2.2.2
    Final timings for group 0 on channel 0: 1.10.7
    Lower bound for group 1 on channel 0: 1.6.1
    Upper bound for group 1 on channel 0: 2.0.2
    Final timings for group 1 on channel 0: 1.9.1
    Lower bound for group 2 on channel 0: 2.0.7
    Upper bound for group 2 on channel 0: 2.8.1
    Final timings for group 2 on channel 0: 2.4.4
    Lower bound for group 3 on channel 0: 2.4.7
    Upper bound for group 3 on channel 0: 3.0.0
    Final timings for group 3 on channel 0: 2.8.3
    [...]
    
    Final timings are always the average of the two bounds. The last dots
    separate eights (not decimals) and the middles are elenvenths or twelfths
    depending on the clock speed (twelfths in this case).
    
    Change-Id: Idb7c84b514716c7265b94890c39b7225de7800dc
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
    Reviewed-on: http://review.coreboot.org/3257
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/3257 for details.

-gerrit