[coreboot-gerrit] Patch set updated for coreboot: b180dd9 Intel 945, 5000, Sandy Bridge: Unify `udelay.c`

Nico Huber (nico.huber@secunet.com) gerrit at coreboot.org
Fri May 17 16:20:05 CEST 2013


Nico Huber (nico.huber at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3220

-gerrit

commit b180dd9fe8a75173c73858a46a1bff348affd44d
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Wed May 8 17:08:55 2013 +0200

    Intel 945, 5000, Sandy Bridge: Unify `udelay.c`
    
    1. Change the comparison from < to <= as done for Sandy Bridge. This
       is quite controversial and is going to get split out, when Stefan
       enlightens us all, why he used <= instead of <.
    2. Use the same indentation and comment placement.
       (Run `indent -linux …` too.)
    3. Use the same spelling of words.
    
    Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 src/northbridge/intel/i945/udelay.c        | 7 +++----
 src/northbridge/intel/sandybridge/udelay.c | 4 ++--
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index 3d5d6c6..b342222 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -24,7 +24,7 @@
 #include <cpu/intel/speedstep.h>
 
 /**
- * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
+ * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock
  */
 
 void udelay(u32 us)
@@ -63,7 +63,7 @@ void udelay(u32 us)
 	msr = rdmsr(0x198);
 	divisor = (msr.hi >> 8) & 0x1f;
 
-	d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */
+	d = (fsb * divisor) / 4;	/* CPU clock is always a quarter. */
 
 	multiply_to_tsc(&tscd, us, d);
 
@@ -78,6 +78,5 @@ void udelay(u32 us)
 	do {
 		tsc = rdtsc();
 	} while ((tsc.hi < tsc1.hi)
-		 || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
-
+		 || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo)));
 }
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
index a2ce0d8..670898a 100644
--- a/src/northbridge/intel/sandybridge/udelay.c
+++ b/src/northbridge/intel/sandybridge/udelay.c
@@ -23,7 +23,7 @@
 #include <cpu/x86/msr.h>
 
 /**
- * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz
+ * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz
  */
 
 void udelay(u32 us)
@@ -37,7 +37,7 @@ void udelay(u32 us)
 	msr = rdmsr(0xce);
 	divisor = (msr.lo >> 8) & 0xff;
 
-	d = fsb * divisor; /* On Core/Core2 this is divided by 4 */
+	d = fsb * divisor;	/* On Core/Core2 this is divided by 4 */
 	multiply_to_tsc(&tscd, us, d);
 
 	tsc1 = rdtsc();



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