[coreboot-gerrit] New patch to review for coreboot: 8c89f3c intel/gm45: Fix interpretation of VT-d disable bit

[Nico Huber (nico.huber@secunet.com)]

Nico Huber (nico.huber at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3252

-gerrit

commit 8c89f3c1a7d8ee3066b96a45b7ce2e01e07e8dfa
Author: Nico Huber <nico.huber at secunet.com>
Date:   Tue May 14 11:02:43 2013 +0200

    intel/gm45: Fix interpretation of VT-d disable bit
    
    When configuring the GTT size for the integrated graphics, the state
    of VT-d was read wrong. Bit 48 of CAPID0 (D0F0) is set when VT-d is
    _disabled_.
    
    Change-Id: I87582c18f4769c2a05be86936d865c0d1fb35966
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/northbridge/intel/gm45/igd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index d54ee41..0a8f21e 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -67,7 +67,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
 	reg16 = pci_read_config16(mch_dev, D0F0_GGC);
 	reg16 &= 0xf00f;
 	reg16 |= 0x0350;
-	if (capid & (1 << (48 - 32)))
+	if (!(capid & (1 << (48 - 32))))
 		reg16 |= 0x0800;
 	pci_write_config16(mch_dev, D0F0_GGC, reg16);