[coreboot-gerrit] Patch set updated for coreboot: 664d34f Asus F2A85-M Cleanup the PCIe config
David Hendricks (dhendrix@chromium.org)
gerrit at coreboot.org
Mon May 6 07:32:10 CEST 2013
David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3194
-gerrit
commit 664d34fa474d62409c05631b62cf64d3df222701
Author: Rudolf Marek <r.marek at assembler.cz>
Date: Sat May 4 00:08:34 2013 +0200
Asus F2A85-M Cleanup the PCIe config
Document the lane assignment from BKDG datasheet.
Assign the lanes correctly to
the physical slots on the motherboard.
UMI is connected to SB via 4x PCIe bridge 8
blue x16 slot is not shared with DDI and is routed through PCIe bridge 2
black x86 slot is fact x4 slot and uses all 4 GPP from CPU
Assume that DDI is on out-of-PCIe-band lanes.
Change sizeof(type) * 6 to sizeof(variable). I think the cleanup part
may be applied to other boards. Not sure why the copy is needed
instead of direct reference. Maybe it has something to do with CAR?
Change-Id: I44c4c83e6a8e31d6150a602a0993972ac63105bd
Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 133 ++++++++++-----------
.../asus/f2a85-m/PlatformGnbPcieComplex.h | 40 -------
2 files changed, 65 insertions(+), 108 deletions(-)
diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c
index 8ee6707..e47c7bf 100644
--- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c
+++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c
@@ -26,58 +26,75 @@
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
+/*
+
+From fam15h BKDG: Table 45: Lane Id Mapping
+
+Lane Id
+0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
+1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
+2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
+3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
+4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
+5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
+6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
+7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
+8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
+9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
+10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
+11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
+12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
+13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
+14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
+15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
+16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
+17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
+18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
+19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
+20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
+21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
+22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
+23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
+24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
+25 DP0_TX[P,N]1
+26 DP0_TX[P,N]2
+27 DP0_TX[P,N]3
+28 DP1_TX[P,N]0
+29 DP1_TX[P,N]1
+30 DP1_TX[P,N]2
+31 DP1_TX[P,N]3
+32 DP2_TX[P,N]0
+33 DP2_TX[P,N]1
+34 DP2_TX[P,N]2
+35 DP2_TX[P,N]3
+36 DP2_TX[P,N]4
+37 DP2_TX[P,N]5
+38 DP2_TX[P,N]6
+*/
+
PCIe_PORT_DESCRIPTOR PortList [] = {
- /* PCIe port, Lanes 8:23, PCI Device Number 2 */
+ /* PCIe port, Lanes 8:23, PCI Device Number 2 blue x16 slot */
{
0, /* Descriptor flags */
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
- /* PCIe port, Lanes 16:23, PCI Device Number 3 */
- {
- 0, /* Descriptor flags */
- PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23),
- PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
- },
-
- /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
+ /* PCIe port, Lanes 4, PCI Device Number 4, black x16 slot (in fact x4) */
{
0, /* Descriptor flags */
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
-
- /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
- {
- 0, /* Descriptor flags */
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
- },
-
- /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1, TODO: Disabled. */
- {
- 0, /* Descriptor flags */
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
- },
-
- /* PCIe port, Lanes 7, PCI Device Number 7, LAN , TODO: not the last entry.*/
- {
- 0, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
- },
-
-#if 1
- /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */
+ /* Initialize Port descriptor (PCIe port, Lanes 4 UMI link to SB, PCI Device Number 8 */
{
DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
},
-#endif
};
+ /* this is not known if it is completely correct VGA/DVI works, HDMI untested */
+
PCIe_DDI_DESCRIPTOR DdiList [] = {
// DP0 to HDMI0/DP
{
@@ -94,29 +111,9 @@ PCIe_DDI_DESCRIPTOR DdiList [] = {
// DP2 to HDMI1/DP
{
0,
-// PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 32, 38),
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35),
- //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3)
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3)
},
- // GFX Lane 15-12
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4)
- },
- // GFX Lane 11-8
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5)
- },
- // GFX Lane 7-4
- {
- DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6)
- }
};
PCIe_COMPLEX_DESCRIPTOR Trinity = {
@@ -159,9 +156,9 @@ OemCustomizeInitEarly (
//
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
- AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) +
- sizeof (PCIe_PORT_DESCRIPTOR) * 7 +
- sizeof (PCIe_DDI_DESCRIPTOR)) * 6;
+ AllocHeapParams.RequestedBufferSize = sizeof (Trinity) +
+ sizeof (DdiList) +
+ sizeof (PortList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
@@ -174,33 +171,33 @@ OemCustomizeInitEarly (
TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
+ AllocHeapParams.BufferPtr += sizeof (Trinity);
TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7;
+ AllocHeapParams.BufferPtr += sizeof (PortList);
TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (TrinityPcieComplexListPtr,
0,
- sizeof (PCIe_COMPLEX_DESCRIPTOR),
+ sizeof (Trinity),
&InitEarly->StdHeader);
LibAmdMemFill (TrinityPciePortPtr,
0,
- sizeof (PCIe_PORT_DESCRIPTOR) * 7,
+ sizeof (PortList),
&InitEarly->StdHeader);
LibAmdMemFill (TrinityPcieDdiPtr,
0,
- sizeof (PCIe_DDI_DESCRIPTOR) * 6,
+ sizeof (DdiList),
&InitEarly->StdHeader);
- LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
- LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader);
- LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader);
+ LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (Trinity), &InitEarly->StdHeader);
+ LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PortList), &InitEarly->StdHeader);
+ LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (DdiList), &InitEarly->StdHeader);
- ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
- ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
+ ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
+ ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
}
diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h
index 3f14805..b3c69cf 100644
--- a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h
+++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h
@@ -24,46 +24,6 @@
#include "AGESA.h"
#include "amdlib.h"
-//GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
-//GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
-#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
- //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
-
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
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