[coreboot-gerrit] New patch to review for coreboot: 64caa69 AMD: Use `static const` instead of `const static`

Paul Menzel (paulepanter@users.sourceforge.net) gerrit at coreboot.org
Sat May 4 18:14:41 CEST 2013


Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3197

-gerrit

commit 64caa695240720a590b7af07885b5229946ef6cc
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Sat May 4 18:07:13 2013 +0200

    AMD: Use `static const` instead of `const static`
    
    From ISO C99 standard: »The placement of a storage-class specifier
    other than at the beginning of the declaration specifiers in a
    declaration is an obsolescent feature.«
    
    Found at <http://www.approxion.com/?p=41>.
    
    The following command was used to make the change.
    
        $ git grep -l 'const static' src/ | xargs sed -i 's/const static/static const/'
    
    The same change was done already for AMD Persimmon in the following
    commit.
    
        commit 824e192809e021b3cdee947a44b3a18d276bdb35
        Author: Jens Rottmann <JRottmann at LiPPERTembedded.de>
        Date:   Wed Feb 20 21:24:20 2013 +0100
    
            Persimmon: platform_cfg.h: Declare codec arrays as `static const`
    
            Reviewed-on: http://review.coreboot.org/2474
    
    Change-Id: I233c83fdc95ea4f83f7296c818547beb52366a3d
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 src/northbridge/amd/amdmct/mct/mctdqs_d.c      |  4 ++--
 src/northbridge/amd/amdmct/mct/mctsrc.c        |  6 +++---
 src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |  4 ++--
 src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c   |  6 +++---
 src/vendorcode/amd/cimx/sb800/AZALIA.c         | 16 ++++++++--------
 src/vendorcode/amd/cimx/sb800/ECfanc.c         |  6 +++---
 src/vendorcode/amd/cimx/sb800/SATA.c           |  6 +++---
 src/vendorcode/amd/cimx/sb800/SBCMN.c          |  8 ++++----
 src/vendorcode/amd/cimx/sb800/SBPOR.c          |  4 ++--
 9 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 0e2a43f..ab1347a 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -84,7 +84,7 @@ static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32
 }
 
 /*Warning:  These must be located so they do not cross a logical 16-bit segment boundary!*/
-const static u32 TestPatternJD1a_D[] = {
+static const u32 TestPatternJD1a_D[] = {
 	0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, /* QW0-1, ALL-EVEN */
 	0x00000000,0x00000000,0x00000000,0x00000000, /* QW2-3, ALL-EVEN */
 	0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, /* QW4-5, ALL-EVEN */
@@ -122,7 +122,7 @@ const static u32 TestPatternJD1a_D[] = {
 	0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, /* QW4-5, DQ7-ODD */
 	0x80808080,0x80808080,0x80808080,0x80808080  /* QW6-7, DQ7-ODD */
 };
-const static u32 TestPatternJD1b_D[] = {
+static const u32 TestPatternJD1b_D[] = {
 	0x00000000,0x00000000,0x00000000,0x00000000, /* QW0,CHA-B, ALL-EVEN */
 	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, /* QW1,CHA-B, ALL-EVEN */
 	0x00000000,0x00000000,0x00000000,0x00000000, /* QW2,CHA-B, ALL-EVEN */
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c
index 4280645..feb4170 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c
@@ -50,19 +50,19 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat);
 
 /* Warning:  These must be located so they do not cross a logical 16-bit
    segment boundary! */
-const static u32 TestPattern0_D[] = {
+static const u32 TestPattern0_D[] = {
 	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa,
 	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa,
 	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa,
 	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa,
 };
-const static u32 TestPattern1_D[] = {
+static const u32 TestPattern1_D[] = {
 	0x55555555, 0x55555555, 0x55555555, 0x55555555,
 	0x55555555, 0x55555555, 0x55555555, 0x55555555,
 	0x55555555, 0x55555555, 0x55555555, 0x55555555,
 	0x55555555, 0x55555555, 0x55555555, 0x55555555,
 };
-const static u32 TestPattern2_D[] = {
+static const u32 TestPattern2_D[] = {
 	0x12345678, 0x87654321, 0x23456789, 0x98765432,
 	0x59385824, 0x30496724, 0x24490795, 0x99938733,
 	0x40385642, 0x38465245, 0x29432163, 0x05067894,
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 4f4870c..76d01da 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -92,7 +92,7 @@ static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32
 }
 
 /*Warning:  These must be located so they do not cross a logical 16-bit segment boundary!*/
-const static u32 TestPatternJD1a_D[] = {
+static const u32 TestPatternJD1a_D[] = {
 	0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, /* QW0-1, ALL-EVEN */
 	0x00000000,0x00000000,0x00000000,0x00000000, /* QW2-3, ALL-EVEN */
 	0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, /* QW4-5, ALL-EVEN */
@@ -130,7 +130,7 @@ const static u32 TestPatternJD1a_D[] = {
 	0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, /* QW4-5, DQ7-ODD */
 	0x80808080,0x80808080,0x80808080,0x80808080  /* QW6-7, DQ7-ODD */
 };
-const static u32 TestPatternJD1b_D[] = {
+static const u32 TestPatternJD1b_D[] = {
 	0x00000000,0x00000000,0x00000000,0x00000000, /* QW0,CHA-B, ALL-EVEN */
 	0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, /* QW1,CHA-B, ALL-EVEN */
 	0x00000000,0x00000000,0x00000000,0x00000000, /* QW2,CHA-B, ALL-EVEN */
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index c60cefb..6189608 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -49,19 +49,19 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat);
 
 /* Warning:  These must be located so they do not cross a logical 16-bit
    segment boundary! */
-const static u32 TestPattern0_D[] = {
+static const u32 TestPattern0_D[] = {
 	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa,
 	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa,
 	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa,
 	0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa,
 };
-const static u32 TestPattern1_D[] = {
+static const u32 TestPattern1_D[] = {
 	0x55555555, 0x55555555, 0x55555555, 0x55555555,
 	0x55555555, 0x55555555, 0x55555555, 0x55555555,
 	0x55555555, 0x55555555, 0x55555555, 0x55555555,
 	0x55555555, 0x55555555, 0x55555555, 0x55555555,
 };
-const static u32 TestPattern2_D[] = {
+static const u32 TestPattern2_D[] = {
 	0x12345678, 0x87654321, 0x23456789, 0x98765432,
 	0x59385824, 0x30496724, 0x24490795, 0x99938733,
 	0x40385642, 0x38465245, 0x29432163, 0x05067894,
diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c
index edd335f..0f57de6 100644
--- a/src/vendorcode/amd/cimx/sb800/AZALIA.c
+++ b/src/vendorcode/amd/cimx/sb800/AZALIA.c
@@ -61,7 +61,7 @@ VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN
  *
  *
  */
-const static CODECENTRY AzaliaCodecAlc882Table[] =
+static const CODECENTRY AzaliaCodecAlc882Table[] =
 {
   {0x14, 0x01014010},
   {0x15, 0x01011012},
@@ -84,7 +84,7 @@ const static CODECENTRY AzaliaCodecAlc882Table[] =
  *
  *
  */
-const static CODECENTRY AzaliaCodecAlc262Table[] =
+static const CODECENTRY AzaliaCodecAlc262Table[] =
 {
   {0x14, 0x01014010},
   {0x15, 0x411111F0},
@@ -106,7 +106,7 @@ const static CODECENTRY AzaliaCodecAlc262Table[] =
  *
  *
  */
-const static CODECENTRY AzaliaCodecAlc269Table[] =
+static const CODECENTRY AzaliaCodecAlc269Table[] =
 {
   {0x12, 0x99A30960},
   {0x14, 0x99130110},
@@ -129,7 +129,7 @@ const static CODECENTRY AzaliaCodecAlc269Table[] =
  *
  *
  */
-const static CODECENTRY AzaliaCodecAlc861Table[] =
+static const CODECENTRY AzaliaCodecAlc861Table[] =
 {
   {0x01, 0x8086C601},
   {0x0B, 0x01014110},
@@ -152,7 +152,7 @@ const static CODECENTRY AzaliaCodecAlc861Table[] =
  *
  *
  */
-const static CODECENTRY AzaliaCodecAlc889Table[] =
+static const CODECENTRY AzaliaCodecAlc889Table[] =
 {
   {0x11, 0x411111F0},
   {0x14, 0x01014010},
@@ -176,7 +176,7 @@ const static CODECENTRY AzaliaCodecAlc889Table[] =
  *
  *
  */
-const static CODECENTRY AzaliaCodecAd1984Table[] =
+static const CODECENTRY AzaliaCodecAd1984Table[] =
 {
   {0x11, 0x0221401F},
   {0x12, 0x90170110},
@@ -198,7 +198,7 @@ const static CODECENTRY AzaliaCodecAd1984Table[] =
  *
  *
  */
-const static CODECENTRY FrontPanelAzaliaCodecTableList[] =
+static const CODECENTRY FrontPanelAzaliaCodecTableList[] =
 {
   {0x19, 0x02A19040},
   {0x1b, 0x02214020},
@@ -211,7 +211,7 @@ const static CODECENTRY FrontPanelAzaliaCodecTableList[] =
  *
  *
  */
-const static CODECTBLLIST azaliaCodecTableList[] =
+static const CODECTBLLIST azaliaCodecTableList[] =
 {
   {0x010ec0880, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
   {0x010ec0882, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},
diff --git a/src/vendorcode/amd/cimx/sb800/ECfanc.c b/src/vendorcode/amd/cimx/sb800/ECfanc.c
index 8c83059..ac6304d 100644
--- a/src/vendorcode/amd/cimx/sb800/ECfanc.c
+++ b/src/vendorcode/amd/cimx/sb800/ECfanc.c
@@ -40,7 +40,7 @@
  *
  *
  */
-const static UINT8 FunctionNumber[] =
+static const UINT8 FunctionNumber[] =
 {
   Fun_81,
   Fun_83,
@@ -55,7 +55,7 @@ const static UINT8 FunctionNumber[] =
  *
  *
  */
-const static UINT8 MaxZone[] =
+static const UINT8 MaxZone[] =
 {
   4,
   4,
@@ -70,7 +70,7 @@ const static UINT8 MaxZone[] =
  *
  *
  */
-const static UINT8 MaxRegister[] =
+static const UINT8 MaxRegister[] =
 {
   MSG_REG9,
   MSG_REGB,
diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c
index 5966ec8..dc77702 100644
--- a/src/vendorcode/amd/cimx/sb800/SATA.c
+++ b/src/vendorcode/amd/cimx/sb800/SATA.c
@@ -176,7 +176,7 @@ shutdownUnconnectedSataPortClock (
  *
  *
  */
-const static UINT32 sataIfCodeTable[] =
+static const UINT32 sataIfCodeTable[] =
 {
   0x01018F40, //sata class ID of IDE
   0x01040040, //sata class ID of RAID
@@ -192,7 +192,7 @@ const static UINT32 sataIfCodeTable[] =
  *
  *
  */
-const static UINT16 sataDeviceIDTable[] =
+static const UINT16 sataDeviceIDTable[] =
 {
   0x4390,  //sata device ID of IDE
   0x4392,  //sata device ID of RAID
@@ -208,7 +208,7 @@ const static UINT16 sataDeviceIDTable[] =
  *
  *
  */
-const static SATAPHYSETTING sataPhyTable[] =
+static const SATAPHYSETTING sataPhyTable[] =
 {
   {0x3006, 0x0056A607},
   {0x2006, 0x00061400},
diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c
index ea1c029..2e66fe8 100644
--- a/src/vendorcode/amd/cimx/sb800/SBCMN.c
+++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c
@@ -83,7 +83,7 @@ VOID sbUsbPhySetting (IN  UINT32 Value);
  * sbEarlyPostByteInitTable - PCI device registers initial during early POST.
  *
  */
-const static REG8MASK sbEarlyPostByteInitTable[] =
+static const REG8MASK sbEarlyPostByteInitTable[] =
 {
   // SMBUS Device (Bus 0, Dev 20, Func 0)
   {0x00, SMBUS_BUS_DEV_FUN, 0},
@@ -134,7 +134,7 @@ const static REG8MASK sbEarlyPostByteInitTable[] =
  * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST.
  *
  */
-const static AcpiRegWrite sbPmioEPostInitTable[] =
+static const AcpiRegWrite sbPmioEPostInitTable[] =
 {
   // HPET workaround
   {PMIO_BASE >> 8,  SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},
@@ -251,7 +251,7 @@ const static AcpiRegWrite sbPmioEPostInitTable[] =
  * abTblEntry800 - AB-Link Configuration Table for SB800
  *
  */
-const static ABTBLENTRY abTblEntry800[] =
+static const ABTBLENTRY abTblEntry800[] =
 {
   // RPR Enable downstream posted transactions to pass non-posted transactions.
   {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},
@@ -297,7 +297,7 @@ const static ABTBLENTRY abTblEntry800[] =
  * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature
  *
  */
-const static ABTBLENTRY SbPcieOrderRule[] =
+static const ABTBLENTRY SbPcieOrderRule[] =
 {
 // abPostPassNpDownStreamTbl
   {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31},
diff --git a/src/vendorcode/amd/cimx/sb800/SBPOR.c b/src/vendorcode/amd/cimx/sb800/SBPOR.c
index daf13c7..054c73d 100644
--- a/src/vendorcode/amd/cimx/sb800/SBPOR.c
+++ b/src/vendorcode/amd/cimx/sb800/SBPOR.c
@@ -49,7 +49,7 @@
 /**
  * sbPorInitPciTable - PCI device registers initial during the power on stage.
  */
-const static REG8MASK sbPorInitPciTable[] =
+static const REG8MASK sbPorInitPciTable[] =
 {
   // SATA device
   {0x00, SATA_BUS_DEV_FUN, 0},
@@ -82,7 +82,7 @@ const static REG8MASK sbPorInitPciTable[] =
 /**
  * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
  */
-const static AcpiRegWrite sbPmioPorInitTable[] =
+static const AcpiRegWrite sbPmioPorInitTable[] =
 {
   {PMIO_BASE >> 8,  SB_PMIOA_REG5D, 0x00, BIT0},
   {PMIO_BASE >> 8,  SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},



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