[coreboot-gerrit] Patch set updated for coreboot: 834d93a x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c`
Paul Menzel (paulepanter@users.sourceforge.net)
gerrit at coreboot.org
Fri May 3 22:42:25 CEST 2013
Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3184
-gerrit
commit 834d93aa15b9a4f5c2af8eff2306ed5800ef0956
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date: Tue Apr 23 14:49:41 2013 +0200
x86 I/O APIC: Move dumping of I/O APIC regs to `ioapic.c`
Moving the code from the southbridges to `src/arch/x86/lib/ioapic.c`
all boards using the function `set_ioapic_id()` get the debug feature.
Change-Id: Ic59c4c2213ed97bdf3798b3dc6e7cecc30e135d8
Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
src/arch/x86/lib/ioapic.c | 7 +++++++
src/southbridge/intel/bd82x6x/lpc.c | 6 ------
src/southbridge/intel/i82801gx/lpc.c | 7 -------
src/southbridge/intel/lynxpoint/lpc.c | 6 ------
4 files changed, 7 insertions(+), 19 deletions(-)
diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c
index 4964af6..7fb25ba 100644
--- a/src/arch/x86/lib/ioapic.c
+++ b/src/arch/x86/lib/ioapic.c
@@ -77,6 +77,7 @@ void clear_ioapic(u32 ioapic_base)
void set_ioapic_id(u32 ioapic_base, u8 ioapic_id)
{
u32 bsp_lapicid = lapicid();
+ int i;
printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n",
ioapic_base);
@@ -90,6 +91,12 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id)
(io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) |
(ioapic_id << 24));
}
+
+ printk(BIOS_SPEW, "IOAPIC: Dumping registers\n");
+ for (i = 0; i < 3; i++)
+ printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i,
+ io_apic_read(ioapic_base, i));
+
}
static void load_vectors(u32 ioapic_base)
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 3e5b653..bb47dc6 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -60,7 +60,6 @@ static void pch_enable_acpi(struct device *dev)
*/
static void pch_enable_ioapic(struct device *dev)
{
- int i;
u32 reg32;
set_ioapic_id(IO_APIC_ADDR, 0x02);
@@ -69,11 +68,6 @@ static void pch_enable_ioapic(struct device *dev)
reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
io_apic_write(IO_APIC_ADDR, reg32);
- printk(BIOS_SPEW, "IOAPIC: Dumping registers\n");
- for (i = 0; i < 3; i++)
- printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i,
- io_apic_read(ioapic_base, i));
-
io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */
0x01); /* Use Processor System Bus to deliver interrupts. */
}
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 9d6224b..9285080 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -46,18 +46,11 @@ typedef struct southbridge_intel_i82801gx_config config_t;
*/
static void i82801gx_enable_ioapic(struct device *dev)
{
- int i;
-
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
set_ioapic_id(IO_APIC_ADDR, 0x02);
- printk(BIOS_SPEW, "IOAPIC: Dumping registers\n");
- for (i = 0; i < 3; i++)
- printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i,
- io_apic_read(ioapic_base, i));
-
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 2d1bd5e..35181ae 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -64,7 +64,6 @@ static void pch_enable_acpi(struct device *dev)
*/
static void pch_enable_ioapic(struct device *dev)
{
- int i;
u32 reg32;
set_ioapic_id(IO_APIC_ADDR, 0x02);
@@ -73,11 +72,6 @@ static void pch_enable_ioapic(struct device *dev)
reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
io_apic_write(IO_APIC_ADDR, reg32);
- printk(BIOS_SPEW, "IOAPIC: Dumping registers\n");
- for (i = 0; i < 3; i++)
- printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i,
- io_apic_read(ioapic_base, i));
-
io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */
0x01); /* Use Processor System Bus to deliver interrupts. */
}
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