[coreboot-gerrit] New patch to review for coreboot: da8d329 Intel 82801Gx: LPC: Unify I/O APIC setup
Paul Menzel (paulepanter@users.sourceforge.net)
gerrit at coreboot.org
Fri May 3 12:50:49 CEST 2013
Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3181
-gerrit
commit da8d329c5f7ceee820f20e68cc2b7e3646ad540b
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date: Tue Apr 23 14:40:23 2013 +0200
Intel 82801Gx: LPC: Unify I/O APIC setup
Remove local copies of reading and writing I/O APIC registers by
using already available functions.
This change is similar to
commit db4f875a412e6c41f48a86a79b72465f6cd81635
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Jan 31 17:24:12 2012 +0200
IOAPIC: Divide setup_ioapic() in two parts.
Reviewed-on: http://review.coreboot.org/300
and
commit e614353194c712a40aa8444a530b2062876eabe3
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Feb 26 17:24:41 2013 +0200
Unify setting 82801a/b/c/d IOAPIC ID
Reviewed-on: http://review.coreboot.org/2532
and uses `io_apic_read()` and `io_apic_write()` too.
Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356
Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
src/southbridge/intel/i82801gx/lpc.c | 58 +++++++++++++++++++-----------------
1 file changed, 31 insertions(+), 27 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 777a6d7..8be8afc 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -39,37 +39,38 @@
typedef struct southbridge_intel_i82801gx_config config_t;
-static void i82801gx_enable_apic(struct device *dev)
+/**
+ * Enable ACPI I/O range.
+ *
+ * @param dev PCI device with ACPI and PM BAR's
+ */
+static void i82801gx_enable_acpi(struct device *dev)
{
- int i;
- u32 reg32;
- volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
- volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+ /* Set ACPI base address (I/O space). */
+ /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */
- /* Enable ACPI I/O and power management.
- * Set SCI IRQ to IRQ9
- */
+ /* Enable ACPI I/O range decode and ACPI power management. */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+}
- *ioapic_index = 0;
- *ioapic_data = (2 << 24);
-
- *ioapic_index = 0;
- reg32 = *ioapic_data;
- printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
- if (reg32 != (2 << 24))
- die("APIC Error\n");
-
- printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
- for (i=0; i<3; i++) {
- *ioapic_index = i;
- printk(BIOS_SPEW, " reg 0x%04x:", i);
- reg32 = *ioapic_data;
- printk(BIOS_SPEW, " 0x%08x\n", reg32);
- }
+/**
+ * Set miscellanous static southbridge features.
+ *
+ * @param dev PCI device with I/O APIC control registers
+ */
+static void i82801gx_enable_ioapic(struct device *dev)
+{
+ int i;
- *ioapic_index = 3; /* Select Boot Configuration register. */
- *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+ set_ioapic_id(IO_APIC_ADDR, 0x02);
+
+ printk(BIOS_SPEW, "IOAPIC: Dumping registers\n");
+ for (i = 0; i < 3; i++)
+ printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i,
+ io_apic_read(ioapic_base, i));
+
+ io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */
+ 0x01); /* Use Processor System Bus to deliver interrupts. */
}
static void i82801gx_enable_serial_irqs(struct device *dev)
@@ -421,8 +422,11 @@ static void lpc_init(struct device *dev)
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ /* ACPI initialization. */
+ i82801gx_enable_acpi(dev);
+
/* IO APIC initialization. */
- i82801gx_enable_apic(dev);
+ i82801gx_enable_ioapic(dev);
i82801gx_enable_serial_irqs(dev);
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