[coreboot-gerrit] New patch to review for coreboot: c81c69a Enable the SD controller for F2A85-M

[Rudolf Marek (r.marek@assembler.cz)]

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3167

-gerrit

commit c81c69ad4aedbeef72df649efdaf16dc4304c35d
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Wed May 1 22:29:13 2013 +0200

    Enable the SD controller for F2A85-M
    
    If the SD controller is "off" hudson.c won't disable that.
    The PCI device is still visible and PCI BAR will be allocated
    by Linux. Unfortunately it may happen that the particular address
    is used by non-standard BAR for SPI controller.
    
    Change-Id: Ied7c581727541e2c81b0b1c2b70fd32de0014730
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 src/mainboard/asus/f2a85-m/devicetree.cb | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb
index 8272964..0014381 100644
--- a/src/mainboard/asus/f2a85-m/devicetree.cb
+++ b/src/mainboard/asus/f2a85-m/devicetree.cb
@@ -102,7 +102,8 @@ chip northbridge/amd/agesa/family15tn/root_complex
 				device pci 14.4 on  end # PCI	0x4384 # PCI-b conflict with GPIO.
 				device pci 14.5 on  end # USB 2
 				device pci 14.6 off end # Gec
-				device pci 14.7 off end
+				# SD, make it on so the BAR is assigned (if proper hudson on/off handling is implemented this may go away)
+				device pci 14.7 on end
 				device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
 				device pci 15.1 on end # PCIe 1 onboard gigabit
 				device pci 15.2 off end # unused