[coreboot-gerrit] New patch to review for coreboot: e91d920 boot: add disable_cache_rom() function

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2980

-gerrit

commit e91d920c248d18f99af1ef602b9c98ffc53bf3ba
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Mar 29 16:23:23 2013 -0500

    boot: add disable_cache_rom() function
    
    On certain architectures such as x86 the bootstrap processor
    does most of the work. When CACHE_ROM is employed it's appropriate
    to ensure that the caching enablement of the ROM is disabled so that
    the caching settings are symmetric before booting the payload or OS.
    
    Tested this on an x86 machine that turned on ROM caching. Linux did not
    complain about asymmetric MTRR settings nor did the ROM show up as
    cached in the MTRR settings.
    
    Change-Id: Ia32ff9fdb1608667a0e9a5f23b9c8af27d589047
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/arch/x86/boot/acpi.c | 4 ++++
 src/cpu/x86/mtrr/mtrr.c  | 6 ++++++
 src/include/cpu/cpu.h    | 3 +++
 src/lib/selfboot.c       | 5 +++++
 4 files changed, 18 insertions(+)

diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index b04cbe5..7b207b4 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -646,6 +646,10 @@ void suspend_resume(void)
 #if CONFIG_COVERAGE
 		coverage_exit();
 #endif
+		/* Tear down the caching of the ROM. */
+		if (disable_cache_rom)
+			disable_cache_rom();
+
 		post_code(POST_OS_RESUME);
 		acpi_jump_to_wakeup(wake_vec);
 	}
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 253a7c3..6089127 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -29,6 +29,7 @@
 #include <string.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
@@ -406,6 +407,11 @@ void x86_mtrr_disable_rom_caching(void)
 	wrmsr(MTRRphysBase_MSR(index), msr_val);
 	enable_cache();
 }
+
+void disable_cache_rom(void)
+{
+	x86_mtrr_disable_rom_caching();
+}
 #endif
 
 struct var_mtrr_state {
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
index bed77de..a2272f3 100644
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@@ -9,6 +9,9 @@ struct bus;
 void initialize_cpus(struct bus *cpu_bus);
 void asmlinkage secondary_cpu_init(unsigned int cpu_index);
 
+/* If a ROM cache was set up disable it before jumping to the payload or OS. */
+void __attribute__((weak)) disable_cache_rom(void);
+
 #if CONFIG_HAVE_SMI_HANDLER
 void smm_init(void);
 void smm_lock(void);
diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c
index f933142..be03b85 100644
--- a/src/lib/selfboot.c
+++ b/src/lib/selfboot.c
@@ -20,6 +20,7 @@
 
 #include <arch/byteorder.h>
 #include <console/console.h>
+#include <cpu/cpu.h>
 #include <fallback.h>
 #include <boot/elf.h>
 #include <boot/elf_boot.h>
@@ -540,6 +541,10 @@ int selfboot(struct lb_memory *mem, struct cbfs_payload *payload)
 	coverage_exit();
 #endif
 
+	/* Tear down the caching of the ROM. */
+	if (disable_cache_rom)
+		disable_cache_rom();
+
 	/* Before we go off to run the payload, see if
 	 * we stayed within our bounds.
 	 */