[coreboot-gerrit] Patch merged into coreboot/master: e85f4eb armv7: update sync barrier usage in dcache_op_set_way()

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit e85f4eb1b0f63535ceb36315712a03d7d7f656ac
Author: David Hendricks <dhendrix at chromium.org>
Date:   Tue Mar 26 21:34:01 2013 -0700

    armv7: update sync barrier usage in dcache_op_set_way()
    
    This moves the dsb() before the loop to sync any outstanding memory
    accesses, and adds an isb() after the loop to ensure all outstanding
    instructions are completed.
    
    Change-Id: I1a11b39f104ae780370cfd2db3badcf4e91dc017
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    Reviewed-on: http://review.coreboot.org/2929
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Build-Tested: build bot (Jenkins) at Wed Mar 27 09:37:00 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Fri Mar 29 21:12:54 2013, giving +2
See http://review.coreboot.org/2929 for details.

-gerrit