[coreboot-gerrit] Patch merged into coreboot/master: 77a5b40 x86: mtrr: add CONFIG_CACHE_ROM support

gerrit at coreboot.org gerrit at coreboot.org
Fri Mar 29 19:59:55 CET 2013

the following patch was just integrated into master:
commit 77a5b4046ab7e7bee887990b342a7356554fd391
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Mar 26 12:47:47 2013 -0500

    x86: mtrr: add CONFIG_CACHE_ROM support
    The CONFIG_CACHE_ROM support in the MTRR code allocates an MTRR
    specifically for setting up write-protect cachine of the ROM. It is
    assumed that CONFIG_ROM_SIZE is the size of the ROM and the whole
    area should be cached just under 4GiB. If enabled, the MTRR code
    will allocate but not enable rom caching. It is up to the callers
    of the MTRR code to explicitly enable (and disable afterwards) through
    the use of 2 new functions:
    - x86_mtrr_enable_rom_caching()
    - x86_mtrr_disable_rom_caching()
    Additionally, the CACHE_ROM option is exposed to the config menu so
    that it is not just selected by the chipset or board. The reasoning
    is that through a multitude of options CACHE_ROM may not be appropriate
    for enabling.
    Change-Id: I4483df850f442bdcef969ffeaf7608ed70b88085
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/2918
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Build-Tested: build bot (Jenkins) at Fri Mar 29 05:21:00 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Fri Mar 29 19:59:53 2013, giving +2
See http://review.coreboot.org/2918 for details.


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