[coreboot-gerrit] Patch set updated for coreboot: 6618df7 armv7: clean+invalidate all cache levels when disabling MMU
David Hendricks (dhendrix@chromium.org)
gerrit at coreboot.org
Thu Mar 28 22:11:08 CET 2013
David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2930
-gerrit
commit 6618df73349cd1ad6109fb1524334ede725c4cad
Author: David Hendricks <dhendrix at chromium.org>
Date: Tue Mar 26 21:39:03 2013 -0700
armv7: clean+invalidate all cache levels when disabling MMU
This iterates thru all cache levels and cleans + invalidates all
data and unified caches before disabling dcache and MMU.
Change-Id: I8a671b4c90d7b88b8d0a95947bfa17f912cebaa2
Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
src/arch/armv7/lib/cache.c | 33 ++++++++++++++++++++++++++++++---
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c
index c93da36..a879acc 100644
--- a/src/arch/armv7/lib/cache.c
+++ b/src/arch/armv7/lib/cache.c
@@ -207,13 +207,40 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
dcache_op_mva(addr, len, OP_DCCIMVAC);
}
-
void dcache_mmu_disable(void)
{
- uint32_t sctlr;
+ uint32_t sctlr, clidr;
+ int level;
+
+ clidr = read_clidr();
+ for (level = 0; level < 7; level++) {
+ unsigned int ctype = (clidr >> (level * 3)) & 0x7;
+ uint32_t csselr;
+
+ switch(ctype) {
+ case 0x0:
+ /* no cache */
+ break;
+ case 0x2:
+ case 0x4:
+ /* dcache only or unified cache */
+ csselr = level << 1;
+ write_csselr(csselr);
+ dcache_clean_invalidate_all();
+ break;
+ case 0x3:
+ /* separate icache and dcache */
+ csselr = level << 1;
+ write_csselr(csselr);
+ dcache_clean_invalidate_all();
+ break;
+ default:
+ /* reserved */
+ break;
+ }
+ }
sctlr = read_sctlr();
- dcache_clean_invalidate_all();
sctlr &= ~(SCTLR_C | SCTLR_M);
write_sctlr(sctlr);
}
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