[coreboot-gerrit] New patch to review for coreboot: 3282ccc armv7: explicitly select L1 dcache when disabling MMU
David Hendricks (dhendrix@chromium.org)
gerrit at coreboot.org
Wed Mar 27 05:53:27 CET 2013
David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2930
-gerrit
commit 3282cccdc5d27907b44bf11d2c4db0e03513284e
Author: David Hendricks <dhendrix at chromium.org>
Date: Tue Mar 26 21:39:03 2013 -0700
armv7: explicitly select L1 dcache when disabling MMU
This ensures that L1 data cache is selected when disabling the MMU.
Change-Id: I8a671b4c90d7b88b8d0a95947bfa17f912cebaa2
Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
src/arch/armv7/lib/cache.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c
index 3cd0e0a..9bb7649 100644
--- a/src/arch/armv7/lib/cache.c
+++ b/src/arch/armv7/lib/cache.c
@@ -210,13 +210,18 @@ void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
dcache_op_mva(addr, len, OP_DCCIMVAC);
}
-
void dcache_mmu_disable(void)
{
- uint32_t sctlr;
+ uint32_t sctlr, csselr;
+
+ /* ensure L1 data/unified cache is selected */
+ csselr = read_csselr();
+ csselr &= ~0xf;
+ write_csselr(csselr);
- sctlr = read_sctlr();
dcache_clean_invalidate_all();
+
+ sctlr = read_sctlr();
sctlr &= ~(SCTLR_C | SCTLR_M);
write_sctlr(sctlr);
}
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