[coreboot-gerrit] New patch to review for coreboot: 6e93cb7 armv7: added paranoia for cache library

[David Hendricks (dhendrix@chromium.org)]

David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2928

-gerrit

commit 6e93cb75b8dc74cef34e1abbc5e73b76e0315557
Author: David Hendricks <dhendrix at chromium.org>
Date:   Tue Mar 26 21:26:51 2013 -0700

    armv7: added paranoia for cache library
    
    This adds some paranoia to cache manipulation routines:
    - "memory" is added to the clobber list for functions which clean
      and/or invalidate dcache or TLB entries.
    - Remove unneeded clobber list for read_sctlr()
    
    Change-Id: Iaa82ef78bfdad4119f097c3b6db8219f29f832bc
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
 src/arch/armv7/include/arch/cache.h | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h
index 92c0f2b..f074a3b 100644
--- a/src/arch/armv7/include/arch/cache.h
+++ b/src/arch/armv7/include/arch/cache.h
@@ -93,7 +93,7 @@ static inline void isb(void)
 /* invalidate entire data TLB */
 static inline void dtlbiall(void)
 {
-	asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
+	asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0) : "memory");
 }
 
 /* invalidate entire instruction TLB */
@@ -105,7 +105,7 @@ static inline void itlbiall(void)
 /* invalidate entire unified TLB */
 static inline void tlbiall(void)
 {
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
+	asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
 }
 
 /* write data access control register (DACR) */
@@ -147,31 +147,31 @@ static inline void bpiall(void)
 /* data cache clean and invalidate by MVA to PoC */
 static inline void dccimvac(unsigned long mva)
 {
-	asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
+	asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva) : "memory");
 }
 
 /* data cache invalidate by set/way */
 static inline void dccisw(uint32_t val)
 {
-	asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
+	asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val) : "memory");
 }
 
 /* data cache clean by MVA to PoC */
 static inline void dccmvac(unsigned long mva)
 {
-	asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva));
+	asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory");
 }
 
 /* data cache invalidate by MVA to PoC */
 static inline void dcimvac(unsigned long mva)
 {
-	asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
+	asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva) : "memory");
 }
 
 /* data cache invalidate by set/way */
 static inline void dcisw(uint32_t val)
 {
-	asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val));
+	asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val) : "memory");
 }
 
 /* instruction cache invalidate all by PoU */
@@ -223,12 +223,12 @@ static inline void write_csselr(uint32_t val)
 static inline unsigned int read_sctlr(void)
 {
 	unsigned int val;
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) : : "cc");
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val));
 	return val;
 }
 
 /* write system control register (SCTLR) */
-static inline void write_sctlr(unsigned int val)
+static inline void write_sctlr(uint32_t val)
 {
 	asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "cc");
 	isb();