[coreboot-gerrit] New patch to review for coreboot: 2b42a1e armv7: cosmetic changes to dcache_op_mva()

[David Hendricks (dhendrix@chromium.org)]

David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2927

-gerrit

commit 2b42a1e4737000467abd5c07a8ef1bc883b16e09
Author: David Hendricks <dhendrix at chromium.org>
Date:   Tue Mar 26 17:47:05 2013 -0700

    armv7: cosmetic changes to dcache_op_mva()
    
    This is just a cosmetic change to dcache_op_mva() to (hopefully) make
    it a easier to follow and more difficult to screw up.
    
    Change-Id: Ia348b2d58f2f2bf5c3cafabcfba06bc411937dba
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
 src/arch/armv7/lib/cache.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c
index b8f4d88..0e28ac4 100644
--- a/src/arch/armv7/lib/cache.c
+++ b/src/arch/armv7/lib/cache.c
@@ -180,19 +180,21 @@ static unsigned int line_bytes(void)
 static void dcache_op_mva(unsigned long addr,
 		unsigned long len, enum dcache_op op)
 {
-	unsigned long line, i;
+	unsigned long line, linesize;
 
-	line = line_bytes();
+	linesize = line_bytes();
+	line = addr & ~(linesize - 1);
 
 	dsb();
-	for (i = addr & ~(line - 1); i < addr + len; i += line) {
+	while (line < addr + len) {
 		switch(op) {
 		case OP_DCCIMVAC:
-			dccimvac(i);
+			dccimvac(line);
 			break;
 		default:
 			break;
 		}
+		line += linesize;
 	}
 	isb();
 }