[coreboot-gerrit] Patch merged into coreboot/master: 7922b46 lynxpoint: Fix GPIO and PM base reservations

gerrit at coreboot.org gerrit at coreboot.org
Thu Mar 21 23:09:50 CET 2013

the following patch was just integrated into master:
commit 7922b468b51eea58c7238f11b21820b8d3747d6b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Mar 8 16:34:33 2013 -0800

    lynxpoint: Fix GPIO and PM base reservations
    The kernel ACPI was not happy with the Add inside a
    ResourceTemplate (or perhaps within the IO declaration)
    Instead make a buffer of IO reservations and turn _CRS
    into a method that updates the buffer depending on the
    chipset type.
    This adds an \ISLP() method that checks the chipset LPC
    device ID to see if it is -LP or -H.
    It also increases the PM base reservation to 256 bytes
    and moves both GPIO and PM base to above 0x1000 on -LP
    Change-Id: I747b658588a4d8ed15a0134009a7c0d74b3916ba
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/2815
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Tue Mar 19 21:35:10 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Thu Mar 21 23:09:49 2013, giving +2
See http://review.coreboot.org/2815 for details.


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