[coreboot-gerrit] Patch merged into coreboot/master: dbc6fcd inteltool: add initial support for Nehalem
gerrit at coreboot.org
gerrit at coreboot.org
Sun Jun 23 23:36:04 CEST 2013
the following patch was just integrated into master:
commit dbc6fcd021759280c71b0e246c0ede34f4879bac
Author: Stefan Tauner <stefan.tauner at gmx.at>
Date: Thu Jun 20 18:05:06 2013 +0200
inteltool: add initial support for Nehalem
Also, add pretty printing of Westmere's DMI registers (tested on my t410s
by staring at non-zero output values :)
Apparently Nehalem does not have a MEMBAR? But there are some
documented memory controller control registers in PCI configuration
space... left out for now.
The PCIEXBAR is not documented publicly AFAICT, but there is
a similar register on a device on bus 0xFF. phcoder might know more...
Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d
Signed-off-by: Stefan Tauner <stefan.tauner at gmx.at>
Reviewed-on: http://review.coreboot.org/3505
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>
See http://review.coreboot.org/3505 for details.
-gerrit
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