[coreboot-gerrit] New patch to review for coreboot: 05733a2 CBMEM: high_table globals cleanup [NOTFORMERGE]

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Sat Jun 22 20:28:29 CEST 2013


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3518

-gerrit

commit 05733a259a62ffaba4c6844ba9ac820b34981a09
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sat Jun 22 21:27:20 2013 +0300

    CBMEM: high_table globals cleanup [NOTFORMERGE]
    
    Squashed for abuild only.
    
    Change-Id: I910842f51ead98af7a85c20c90dd230e6a6458ed
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/arch/armv7/boot/tables.c                       | 13 +--
 src/arch/x86/boot/tables.c                         | 16 +---
 src/include/cbmem.h                                | 12 ++-
 src/lib/cbmem.c                                    | 93 ++++++++++++++++++----
 src/lib/coreboot_table.c                           |  5 +-
 src/lib/dynamic_cbmem.c                            |  5 ++
 src/mainboard/emulation/qemu-i440fx/memory.c       |  7 +-
 src/mainboard/emulation/qemu-i440fx/northbridge.c  |  4 +-
 src/mainboard/getac/p470/romstage.c                |  5 +-
 src/mainboard/google/butterfly/acpi_tables.c       |  2 +-
 src/mainboard/google/link/acpi_tables.c            |  2 +-
 src/mainboard/google/parrot/acpi_tables.c          |  2 +-
 src/mainboard/google/snow/ramstage.c               | 13 +--
 src/mainboard/google/stout/acpi_tables.c           |  2 +-
 src/mainboard/google/stout/romstage.c              |  3 +-
 src/mainboard/ibase/mb899/romstage.c               |  5 +-
 src/mainboard/intel/d945gclf/romstage.c            |  5 +-
 src/mainboard/intel/emeraldlake2/acpi_tables.c     |  2 +-
 src/mainboard/kontron/986lcd-m/romstage.c          |  5 +-
 src/mainboard/roda/rk886ex/romstage.c              |  5 +-
 src/mainboard/roda/rk9/romstage.c                  |  5 +-
 src/mainboard/samsung/lumpy/acpi_tables.c          |  2 +-
 src/mainboard/samsung/stumpy/acpi_tables.c         |  2 +-
 src/northbridge/amd/agesa/family10/northbridge.c   | 18 +----
 src/northbridge/amd/agesa/family12/northbridge.c   | 23 +-----
 src/northbridge/amd/agesa/family14/northbridge.c   | 22 +----
 src/northbridge/amd/agesa/family15/northbridge.c   | 18 +----
 src/northbridge/amd/agesa/family15tn/northbridge.c | 18 +----
 src/northbridge/amd/amdfam10/northbridge.c         | 18 +----
 src/northbridge/amd/amdk8/northbridge.c            | 18 +----
 src/northbridge/amd/gx1/northbridge.c              |  4 +-
 src/northbridge/amd/gx2/northbridge.c              |  4 +-
 src/northbridge/amd/lx/northbridge.c               |  4 +-
 src/northbridge/intel/e7501/northbridge.c          |  4 +-
 src/northbridge/intel/e7505/northbridge.c          |  4 +-
 src/northbridge/intel/e7520/northbridge.c          |  4 +-
 src/northbridge/intel/e7525/northbridge.c          |  4 +-
 src/northbridge/intel/gm45/northbridge.c           |  4 +-
 src/northbridge/intel/i3100/northbridge.c          |  4 +-
 src/northbridge/intel/i440bx/northbridge.c         |  4 +-
 src/northbridge/intel/i440lx/northbridge.c         |  4 +-
 src/northbridge/intel/i5000/northbridge.c          |  5 +-
 src/northbridge/intel/i82810/northbridge.c         |  4 +-
 src/northbridge/intel/i82830/northbridge.c         |  4 +-
 src/northbridge/intel/i855/northbridge.c           |  4 +-
 src/northbridge/intel/i945/northbridge.c           |  4 +-
 src/northbridge/intel/i945/raminit.c               |  5 --
 src/northbridge/intel/sandybridge/northbridge.c    |  4 +-
 src/northbridge/intel/sandybridge/raminit.c        |  5 --
 src/northbridge/intel/sch/northbridge.c            |  6 +-
 src/northbridge/rdc/r8610/northbridge.c            |  4 +-
 src/northbridge/via/cn400/northbridge.c            |  5 +-
 src/northbridge/via/cn700/northbridge.c            |  5 +-
 src/northbridge/via/cx700/northbridge.c            |  5 +-
 src/northbridge/via/vt8601/northbridge.c           |  5 +-
 src/northbridge/via/vt8623/northbridge.c           |  5 +-
 src/northbridge/via/vx900/early_vx900.c            |  5 --
 src/northbridge/via/vx900/northbridge.c            |  6 +-
 58 files changed, 177 insertions(+), 298 deletions(-)

diff --git a/src/arch/armv7/boot/tables.c b/src/arch/armv7/boot/tables.c
index 0fc7399..de6b6fa 100644
--- a/src/arch/armv7/boot/tables.c
+++ b/src/arch/armv7/boot/tables.c
@@ -29,13 +29,6 @@
 
 #define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
 
-/*
- * TODO: "High" tables are a convention used on x86. Maybe we can
- * clean up that naming at some point.
- */
-uint64_t high_tables_base = 0;
-uint64_t high_tables_size;
-
 void cbmem_arch_init(void)
 {
 }
@@ -44,11 +37,7 @@ struct lb_memory *write_tables(void)
 {
 	unsigned long table_pointer, new_table_pointer;
 
-	if (!high_tables_base) {
-		printk(BIOS_ERR, "ERROR: high_tables_base is not set.\n");
-	}
-
-	printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base);
+	cbmem_base_check();
 
 	post_code(0x9d);
 
diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c
index 6355a1b..461ca62 100644
--- a/src/arch/x86/boot/tables.c
+++ b/src/arch/x86/boot/tables.c
@@ -32,8 +32,6 @@
 #include <lib.h>
 #include <smbios.h>
 
-uint64_t high_tables_base = 0;
-uint64_t high_tables_size;
 
 void cbmem_arch_init(void)
 {
@@ -45,6 +43,7 @@ struct lb_memory *write_tables(void)
 {
 	unsigned long low_table_start, low_table_end;
 	unsigned long rom_table_start, rom_table_end;
+	uint64_t cbmem_base, cbmem_size;
 
 	/* Even if high tables are configured, some tables are copied both to
 	 * the low and the high area, so payloads and OSes don't need to know
@@ -52,15 +51,8 @@ struct lb_memory *write_tables(void)
 	 */
 	unsigned long high_table_pointer;
 
-#if !CONFIG_DYNAMIC_CBMEM
-	if (!high_tables_base) {
-		printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n");
-		// Are there any boards without?
-		// Stepan thinks we should die() here!
-	}
-
-	printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base);
-#endif
+	cbmem_base_check();
+	get_cbmem_table(&cbmem_base, &cbmem_size);
 
 	rom_table_start = 0xf0000;
 	rom_table_end =   0xf0000;
@@ -229,7 +221,7 @@ struct lb_memory *write_tables(void)
 
 		/* Also put a forwarder entry into 0-4K */
 		new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end,
-				high_tables_base, high_table_pointer);
+				cbmem_base, high_table_pointer);
 
 		if (new_high_table_pointer > (high_table_pointer +
 					MAX_COREBOOT_TABLE_SIZE))
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index baec780..4df9a85 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -133,15 +133,21 @@ void cbmem_add_lb_mem(struct lb_memory *mem);
 #else /* !CONFIG_DYNAMIC_CBMEM */
 
 #ifndef __PRE_RAM__
-extern uint64_t high_tables_base, high_tables_size;
+void set_top_of_ram(uint64_t ramtop);
+void set_top_of_ram_once(uint64_t ramtop);
 void set_cbmem_toc(struct cbmem_entry *);
 #endif
 
-void cbmem_init(u64 baseaddr, u64 size);
+void get_high_table(uint64_t *base, uint64_t *size);
+void get_cbmem_table(uint64_t *base, uint64_t *size);
+
 int cbmem_reinit(u64 baseaddr);
 
 extern struct cbmem_entry *get_cbmem_toc(void);
 
+#define high_tables_base(x) ((uint64_t)get_cbmem_toc())
+#define high_tables_base32(x) ((uint32_t)get_cbmem_toc())
+
 #endif /* CONFIG_DYNAMIC_CBMEM */
 
 /* Common API between cbmem and dynamic cbmem. */
@@ -156,6 +162,8 @@ void *cbmem_add(u32 id, u64 size);
 /* Find a cbmem entry of a given id. These return NULL on failure. */
 void *cbmem_find(u32 id);
 
+int cbmem_base_check(void);
+
 #ifndef __PRE_RAM__
 /* Ramstage only functions. */
 void cbmem_list(void);
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 3702da1..0af01f9 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -42,26 +42,73 @@ struct cbmem_entry {
 } __attribute__((packed));
 
 #ifndef __PRE_RAM__
-static struct cbmem_entry *bss_cbmem_toc;
+static uint64_t cbmem_base = 0;
+static uint64_t cbmem_size = 0;
+#endif
 
-struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
+extern unsigned long get_top_of_ram(void);
+
+unsigned long __attribute__((weak)) get_top_of_ram(void)
 {
-	return bss_cbmem_toc;
+	printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n");
+	return 0;
 }
 
+void __attribute__((weak)) get_high_table(uint64_t *base, uint64_t *size)
+{
+	uint64_t top_of_ram = get_top_of_ram();
+	if (top_of_ram >= HIGH_MEMORY_SIZE) {
+		*base = top_of_ram - HIGH_MEMORY_SIZE;
+		*size = HIGH_MEMORY_SIZE;
+	} else {
+		*base = 0;
+		*size = 0;
+	}
+}
+
+#ifndef __PRE_RAM__
 void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x)
 {
 	/* do nothing, this should be called by chipset to save TOC in NVRAM */
 }
-#else
+
+void set_top_of_ram(uint64_t ramtop)
+{
+	cbmem_base = ramtop - HIGH_MEMORY_SIZE;
+	cbmem_size = HIGH_MEMORY_SIZE;
+}
+
+void set_top_of_ram_once(uint64_t ramtop)
+{
+	if (!cbmem_base)
+		set_top_of_ram(ramtop);
+}
+#endif
 
 struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
 {
-	printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n");
-	return NULL;
+#ifdef __PRE_RAM__
+	uint64_t cbmem_base, cbmem_size;
+	get_high_table(&cbmem_base, &cbmem_size);
+#else
+	if (!cbmem_base)
+		get_high_table(&cbmem_base, &cbmem_size);
+#endif
+	return (struct cbmem_entry *) (unsigned)cbmem_base;
 }
 
+void get_cbmem_table(uint64_t *base, uint64_t *size)
+{
+#ifdef __PRE_RAM__
+	get_high_table(base, size);
+#else
+	if (!cbmem_base)
+		get_high_table(&cbmem_base, &cbmem_size);
+
+	*base = cbmem_base;
+	*size = cbmem_size;
 #endif
+}
 
 /**
  * cbmem is a simple mechanism to do some kind of book keeping of the coreboot
@@ -73,13 +120,14 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
  *  - suspend/resume backup memory
  */
 
-void cbmem_init(u64 baseaddr, u64 size)
+static void cbmem_init(u64 baseaddr, u64 size)
 {
 	struct cbmem_entry *cbmem_toc;
 	cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr;
 
 #ifndef __PRE_RAM__
-	bss_cbmem_toc = cbmem_toc;
+	cbmem_base = baseaddr;
+	cbmem_size = size;
 #endif
 
 	printk(BIOS_DEBUG, "Initializing CBMEM area to 0x%llx (%lld bytes)\n",
@@ -113,12 +161,27 @@ int cbmem_reinit(u64 baseaddr)
 	       (unsigned long)baseaddr);
 
 #ifndef __PRE_RAM__
-	bss_cbmem_toc = cbmem_toc;
+	cbmem_base = baseaddr;
 #endif
 
 	return (cbmem_toc[0].magic == CBMEM_MAGIC);
 }
 
+int cbmem_base_check(void)
+{
+	uint64_t base, size;
+
+	get_cbmem_table(&base, &size);
+	if (!base) {
+		printk(BIOS_ERR, "ERROR: cbmem_base is not set.\n");
+		// Are there any boards without?
+		// Stepan thinks we should die() here!
+	}
+	printk(BIOS_DEBUG, "cbmem_base: %llx.\n", base);
+
+	return !!base;
+}
+
 void *cbmem_add(u32 id, u64 size)
 {
 	struct cbmem_entry *cbmem_toc;
@@ -205,25 +268,23 @@ void *cbmem_find(u32 id)
 }
 
 #if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)
+
 /* Returns True if it was not intialized before. */
 int cbmem_initialize(void)
 {
+	uint64_t base = 0, size = 0;
 	int rv = 0;
 
-#ifdef __PRE_RAM__
-	extern unsigned long get_top_of_ram(void);
-	uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
-	uint64_t high_tables_size = HIGH_MEMORY_SIZE;
-#endif
+	get_cbmem_table(&base, &size);
 
 	/* We expect the romstage to always initialize it. */
-	if (!cbmem_reinit(high_tables_base)) {
+	if (!cbmem_reinit(base)) {
 #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
 		/* Something went wrong, our high memory area got wiped */
 		if (acpi_slp_type == 3 || acpi_slp_type == 2)
 			acpi_slp_type = 0;
 #endif
-		cbmem_init(high_tables_base, high_tables_size);
+		cbmem_init(base, size);
 		rv = 1;
 	}
 #ifndef __PRE_RAM__
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index d25b59d..9914b1a 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -542,8 +542,9 @@ unsigned long write_coreboot_table(
 #if CONFIG_DYNAMIC_CBMEM
 	cbmem_add_lb_mem(mem);
 #else /* CONFIG_DYNAMIC_CBMEM */
-	lb_add_memory_range(mem, LB_MEM_TABLE,
-		high_tables_base, high_tables_size);
+	uint64_t base, size;
+	get_cbmem_table(&base, &size);
+	lb_add_memory_range(mem, LB_MEM_TABLE, base, size);
 #endif /* CONFIG_DYNAMIC_CBMEM */
 
 	/* No other memory areas can be added after the memory table has been
diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c
index ba7760d..b753266 100644
--- a/src/lib/dynamic_cbmem.c
+++ b/src/lib/dynamic_cbmem.c
@@ -227,6 +227,11 @@ static int validate_entries(struct cbmem_root *root)
 	return 0;
 }
 
+int cbmem_base_check(void)
+{
+	return 1;
+}
+
 int cbmem_initialize(void)
 {
 	struct cbmem_root *root;
diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c
index 000a0f6..4f9f31c 100644
--- a/src/mainboard/emulation/qemu-i440fx/memory.c
+++ b/src/mainboard/emulation/qemu-i440fx/memory.c
@@ -46,12 +46,7 @@ unsigned long get_top_of_ram(void)
 	return qemu_get_memory_size() * 1024;
 }
 
-#if !CONFIG_DYNAMIC_CBMEM
-struct cbmem_entry *get_cbmem_toc(void)
-{
-	return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
-}
-#else
+#if CONFIG_DYNAMIC_CBMEM
 void *cbmem_top(void)
 {
 	/* Top of cbmem is at lowest usable DRAM address below 4GiB. */
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index 3e45d9a..0afcaed 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -54,9 +54,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 		ram_resource(dev, idx++, 4 * 1024 * 1024, high);
 
 #if !CONFIG_DYNAMIC_CBMEM
-	/* Leave some space for ACPI, PIRQ and MP tables */
-	high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
-	high_tables_size = HIGH_MEMORY_SIZE;
+	set_top_of_ram(tomk * 1024);
 #endif
 
 	/* Reserve space for the IOAPIC.  This should be in the Southbridge,
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 90d38eb..d184ffa 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -358,13 +358,10 @@ void main(unsigned long bist)
 	MCHBAR16(SSKPD) = 0xCAFE;
 
 #if CONFIG_HAVE_ACPI_RESUME
-	/* Start address of high memory tables */
-	unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
-
 	/* If there is no high memory area, we didn't boot before, so
 	 * this is not a resume. In that case we just create the cbmem toc.
 	 */
-	if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
+	if ((boot_mode == 2) && cbmem_reinit(high_tables_base())) {
 		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 
 		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c
index 95b45db..b7bac5d 100644
--- a/src/mainboard/google/butterfly/acpi_tables.c
+++ b/src/mainboard/google/butterfly/acpi_tables.c
@@ -65,7 +65,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 	gnvs->s5u1 = 0;
 
 	/* CBMEM TOC */
-	gnvs->cmem = (u32)get_cbmem_toc();
+	gnvs->cmem = high_tables_base32();
 
 	/* IGD Displays */
 	gnvs->ndid = 3;
diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c
index dbbde68..2b012c4 100644
--- a/src/mainboard/google/link/acpi_tables.c
+++ b/src/mainboard/google/link/acpi_tables.c
@@ -75,7 +75,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs, igd_opregion_t *opregion)
 	gnvs->s5u1 = 0;
 
 	/* CBMEM TOC */
-	gnvs->cmem = (u32)get_cbmem_toc();
+	gnvs->cmem = high_tables_base32();
 
 	/* IGD Displays */
 	gnvs->ndid = 1;
diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c
index 45a9948..9b9ff83 100644
--- a/src/mainboard/google/parrot/acpi_tables.c
+++ b/src/mainboard/google/parrot/acpi_tables.c
@@ -66,7 +66,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 	gnvs->s5u1 = 0;
 
 	/* CBMEM TOC */
-	gnvs->cmem = (u32)get_cbmem_toc();
+	gnvs->cmem = high_tables_base32();
 
 	/* IGD Displays */
 	gnvs->ndid = 3;
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index 72f830d..f51c3a0 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -76,6 +76,13 @@ void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
 	framebuffer->reserved_mask_size = 0;
 }
 
+void get_high_table(uint64_t *base, uint64_t *size)
+{
+	*base = CONFIG_SYS_SDRAM_BASE +
+				((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
+				CONFIG_COREBOOT_TABLES_SIZE;
+	*size = CONFIG_COREBOOT_TABLES_SIZE;
+}
 
 void hardwaremain(void);
 void main(void)
@@ -83,11 +90,7 @@ void main(void)
 	/* FIXME this should be moved elsewhere. We don't want ramstage.c */
 
 	/* set up coreboot tables */
-	high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
-	high_tables_base = CONFIG_SYS_SDRAM_BASE +
-				((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
-				CONFIG_COREBOOT_TABLES_SIZE;
-	cbmem_init(high_tables_base, high_tables_size);
+	cbmem_initialize();
 
 	/* set up dcache and MMU */
 	/* FIXME: this should happen via resource allocator */
diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c
index 62d5891..b4e897b 100644
--- a/src/mainboard/google/stout/acpi_tables.c
+++ b/src/mainboard/google/stout/acpi_tables.c
@@ -69,7 +69,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 	gnvs->s5u1 = 0;
 
 	/* CBMEM TOC */
-	gnvs->cmem = (u32)get_cbmem_toc();
+	gnvs->cmem = high_tables_base32();
 
 	/* IGD Displays */
 	gnvs->ndid = 3;
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 14820dd..476a846 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -313,8 +313,7 @@ void main(unsigned long bist)
 #if CONFIG_EARLY_CBMEM_INIT
 	cbmem_was_initted = !cbmem_initialize();
 #else
-	cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
-						     - HIGH_MEMORY_SIZE));
+	cbmem_was_initted = cbmem_reinit(high_tables_base());
 #endif
 
 #if CONFIG_HAVE_ACPI_RESUME
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 79eaa0b..166c175 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -312,13 +312,10 @@ void main(unsigned long bist)
 	MCHBAR16(SSKPD) = 0xCAFE;
 
 #if CONFIG_HAVE_ACPI_RESUME
-	/* Start address of high memory tables */
-	unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
-
 	/* If there is no high memory area, we didn't boot before, so
 	 * this is not a resume. In that case we just create the cbmem toc.
 	 */
-	if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
+	if ((boot_mode == 2) && cbmem_reinit(high_tables_base())) {
 		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 
 		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index a37f605..3514829 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -270,13 +270,10 @@ void main(unsigned long bist)
 	MCHBAR16(SSKPD) = 0xCAFE;
 
 #if CONFIG_HAVE_ACPI_RESUME
-	/* Start address of high memory tables */
-	unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
-
 	/* If there is no high memory area, we didn't boot before, so
 	 * this is not a resume. In that case we just create the cbmem toc.
 	 */
-	if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
+	if ((boot_mode == 2) && cbmem_reinit(high_tables_base())) {
 		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 
 		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c
index 6e32779..7606788 100644
--- a/src/mainboard/intel/emeraldlake2/acpi_tables.c
+++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c
@@ -88,7 +88,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 	gnvs->s5u1 = 1;
 
 	/* CBMEM TOC */
-	gnvs->cmem = (u32)get_cbmem_toc();
+	gnvs->cmem = high_tables_base32();
 
 	/* IGD Displays */
 	gnvs->ndid = 3;
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 03b24d8..6f6f8da 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -411,13 +411,10 @@ void main(unsigned long bist)
 	MCHBAR16(SSKPD) = 0xCAFE;
 
 #if CONFIG_HAVE_ACPI_RESUME
-	/* Start address of high memory tables */
-	unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
-
 	/* If there is no high memory area, we didn't boot before, so
 	 * this is not a resume. In that case we just create the cbmem toc.
 	 */
-	if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
+	if ((boot_mode == 2) && cbmem_reinit(high_tables_base())) {
 		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 
 		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index ab200d2..0ec4e93 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -347,13 +347,10 @@ void main(unsigned long bist)
 	MCHBAR16(SSKPD) = 0xCAFE;
 
 #if CONFIG_HAVE_ACPI_RESUME
-	/* Start address of high memory tables */
-	unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
-
 	/* If there is no high memory area, we didn't boot before, so
 	 * this is not a resume. In that case we just create the cbmem toc.
 	 */
-	if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
+	if ((boot_mode == 2) && cbmem_reinit(high_tables_base())) {
 		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 
 		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 56eea84..6e4c132 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -184,13 +184,10 @@ void main(unsigned long bist)
 	init_iommu();
 
 #if CONFIG_HAVE_ACPI_RESUME
-	/* Start address of high memory tables */
-	unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
-
 	/* If there is no high memory area, we didn't boot before, so
 	 * this is not a resume. In that case we just create the cbmem toc.
 	 */
-	if (s3resume && cbmem_reinit((u64)high_ram_base)) {
+	if (s3resume && cbmem_reinit(high_tables_base()) {
 		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 
 		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c
index 13e9e0f..1eb8287 100644
--- a/src/mainboard/samsung/lumpy/acpi_tables.c
+++ b/src/mainboard/samsung/lumpy/acpi_tables.c
@@ -88,7 +88,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 	gnvs->s5u1 = 0;
 
 	/* CBMEM TOC */
-	gnvs->cmem = (u32)get_cbmem_toc();
+	gnvs->cmem = high_tables_base32();
 
 	/* IGD Displays */
 	gnvs->ndid = 3;
diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c
index b68edcd..a77190d 100644
--- a/src/mainboard/samsung/stumpy/acpi_tables.c
+++ b/src/mainboard/samsung/stumpy/acpi_tables.c
@@ -89,7 +89,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 	gnvs->s5u1 = 1;
 
 	/* CBMEM TOC */
-	gnvs->cmem = (u32)get_cbmem_toc();
+	gnvs->cmem = high_tables_base32();
 
 	/* IGD Displays */
 	gnvs->ndid = 3;
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index 4589f6d..325d2c1 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -1036,17 +1036,11 @@ static void amdfam10_domain_set_resources(device_t dev)
 					ram_resource(dev, (idx | i), basek, pre_sizek);
 					idx += 0x10;
 					sizek -= pre_sizek;
-					if (high_tables_base==0) {
-					/* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-						high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+					set_top_of_ram_once(uma_memory_base);
 #else
-						high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
+					set_top_of_ram_once(mmio_basek * 1024);
 #endif
-						high_tables_size = HIGH_MEMORY_SIZE;
-						printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
-							     (u32)(high_tables_size / 1024), high_tables_base);
-					}
 				}
 				basek = mmio_basek;
 			}
@@ -1063,15 +1057,11 @@ static void amdfam10_domain_set_resources(device_t dev)
 		idx += 0x10;
 		printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
 			     i, mmio_basek, basek, limitk);
-		if (high_tables_base==0) {
-		/* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-			high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+		set_top_of_ram_once(uma_memory_base);
 #else
-			high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
+		set_top_of_ram_once(limitk * 1024);
 #endif
-			high_tables_size = HIGH_MEMORY_SIZE;
-		}
 	}
 
 #if CONFIG_GFXUMA
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index 621246f..4c230f1 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -722,20 +722,12 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
                     ram_resource(dev, idx, basek, pre_sizek);
                     idx += 0x10;
                     sizek -= pre_sizek;
-                    if (high_tables_base==0) {
-                    /* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-                        high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+                    set_top_of_ram_once(uma_memory_base);
 #else
-                        high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
+                    set_top_of_ram_once(mmio_basek * 1024);
 #endif
-                        high_tables_size = HIGH_MEMORY_SIZE;
-                        printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
-				 (u32)(high_tables_size / 1024),
-                                 high_tables_base);
-                    }
                 }
-
                 basek = mmio_basek;
             }
             if ((basek + sizek) <= 4*1024*1024) {
@@ -751,20 +743,13 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
         idx += 0x10;
         printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
                  0, mmio_basek, basek, limitk);
-        if (high_tables_base==0) {
-        /* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-            high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
-            printk(BIOS_DEBUG, "  adsr - uma_memory_base = %llx.\n", uma_memory_base);
+        set_top_of_ram_once(uma_memory_base);
 #else
-            high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
+        set_top_of_ram_once(limitk * 1024);
 #endif
-            high_tables_size = HIGH_MEMORY_SIZE;
-        }
     }
 	printk(BIOS_DEBUG, "  adsr - mmio_basek = %lx.\n", mmio_basek);
-	printk(BIOS_DEBUG, "  adsr - high_tables_size = %llx.\n",
-		high_tables_size);
 
 #if CONFIG_GFXUMA
 	uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index e7de273..fbf8e44 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -716,19 +716,12 @@ static void domain_set_resources(device_t dev)
 						     pre_sizek);
 					idx += 0x10;
 					sizek -= pre_sizek;
-					if (high_tables_base == 0) {
-						/* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-						high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+					set_top_of_ram_once(uma_memory_base);
 #else
-						high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
+					set_top_of_ram_once(mmio_basek * 1024);
 #endif
-						high_tables_size = HIGH_MEMORY_SIZE;
-						printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
-							 (u32)(high_tables_size / 1024), high_tables_base);
-					}
 				}
-
 				basek = mmio_basek;
 			}
 			if ((basek + sizek) <= 4 * 1024 * 1024) {
@@ -744,20 +737,13 @@ static void domain_set_resources(device_t dev)
 		printk(BIOS_DEBUG,
 			"%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0,
 			 mmio_basek, basek, limitk);
-		if (high_tables_base == 0) {
-			/* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-			high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
-			printk(BIOS_DEBUG, "  adsr - uma_memory_base = %llx.\n", uma_memory_base);
+		set_top_of_ram_once(uma_memory_base);
 #else
-			high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
+		set_top_of_ram_once(limitk * 1024);
 #endif
-			high_tables_size = HIGH_MEMORY_SIZE;
-		}
 	}
 	printk(BIOS_DEBUG, "  adsr - mmio_basek = %lx.\n", mmio_basek);
-	printk(BIOS_DEBUG, "  adsr - high_tables_size = %llx.\n",
-		high_tables_size);
 
 #if CONFIG_GFXUMA
 	uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index 6134830..7e33046 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -807,17 +807,11 @@ static void domain_set_resources(device_t dev)
 					ram_resource(dev, (idx | i), basek, pre_sizek);
 					idx += 0x10;
 					sizek -= pre_sizek;
-					if (high_tables_base==0) {
-						/* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-						high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+					set_top_of_ram_once(uma_memory_base);
 #else
-						high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
+					set_top_of_ram_once(mmio_basek * 1024);
 #endif
-						high_tables_size = HIGH_MEMORY_SIZE;
-						printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
-							 (u32)(high_tables_size / 1024), high_tables_base);
-					}
 				}
 				basek = mmio_basek;
 			}
@@ -834,15 +828,11 @@ static void domain_set_resources(device_t dev)
 		idx += 0x10;
 		printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
 				i, mmio_basek, basek, limitk);
-		if (high_tables_base==0) {
-			/* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-			high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+		set_top_of_ram_once(uma_memory_base);
 #else
-			high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
+		set_top_of_ram_once(limitk * 1024);
 #endif
-			high_tables_size = HIGH_MEMORY_SIZE;
-		}
 	}
 
 #if CONFIG_GFXUMA
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index f91f690..2e1ff2e 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -793,17 +793,11 @@ static void domain_set_resources(device_t dev)
 					ram_resource(dev, (idx | i), basek, pre_sizek);
 					idx += 0x10;
 					sizek -= pre_sizek;
-					if (high_tables_base==0) {
-						/* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-						high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+					set_top_of_ram_once(uma_memory_base);
 #else
-						high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
+					set_top_of_ram_once(mmio_basek * 1024);
 #endif
-						high_tables_size = HIGH_MEMORY_SIZE;
-						printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
-							 (u32)(high_tables_size / 1024), high_tables_base);
-					}
 				}
 				basek = mmio_basek;
 			}
@@ -821,15 +815,11 @@ static void domain_set_resources(device_t dev)
 		idx += 0x10;
 		printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
 				i, mmio_basek, basek, limitk);
-		if (high_tables_base==0) {
-			/* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-			high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+		set_top_of_ram_once(uma_memory_base);
 #else
-			high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
+		set_top_of_ram_once(limitk * 1024);
 #endif
-			high_tables_size = HIGH_MEMORY_SIZE;
-		}
 	}
 
 #if CONFIG_GFXUMA
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 2228fb5..be77f8b 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -1038,17 +1038,11 @@ static void amdfam10_domain_set_resources(device_t dev)
 					idx += 0x10;
 					sizek -= pre_sizek;
 
-					if (high_tables_base==0) {
-					/* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-						high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+					set_top_of_ram_once(uma_memory_base);
 #else
-						high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
+					set_top_of_ram_once(mmio_basek * 1024);
 #endif
-						high_tables_size = HIGH_MEMORY_SIZE;
-						printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
-							HIGH_MEMORY_SIZE / 1024, high_tables_base);
-					}
 				}
 				#if !CONFIG_AMDMCT
 				#if CONFIG_HW_MEM_HOLE_SIZEK != 0
@@ -1076,15 +1070,11 @@ static void amdfam10_domain_set_resources(device_t dev)
 		idx += 0x10;
 		printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
 			     i, mmio_basek, basek, limitk);
-		if (high_tables_base==0) {
-		/* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-			high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+		set_top_of_ram_once(uma_memory_base);
 #else
-			high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
+		set_top_of_ram_once(limitk * 1024);
 #endif
-			high_tables_size = HIGH_MEMORY_SIZE;
-		}
 	}
 
 #if CONFIG_GFXUMA
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 5c1d97a..505d94d 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -1042,17 +1042,11 @@ static void amdk8_domain_set_resources(device_t dev)
 					ram_resource(dev, (idx | i), basek, pre_sizek);
 					idx += 0x10;
 					sizek -= pre_sizek;
-					if (high_tables_base==0) {
-					/* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-						high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+					set_top_of_ram_once(uma_memory_base);
 #else
-						high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
+					set_top_of_ram_once(mmio_basek * 1024);
 #endif
-						high_tables_size = HIGH_MEMORY_SIZE;
-						printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
-							HIGH_MEMORY_SIZE / 1024, high_tables_base);
-					}
 				}
 				#if CONFIG_HW_MEM_HOLE_SIZEK != 0
 				if(reset_memhole)
@@ -1077,15 +1071,11 @@ static void amdk8_domain_set_resources(device_t dev)
 		idx += 0x10;
 		printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
 			     i, mmio_basek, basek, limitk);
-		if (high_tables_base==0) {
-		/* Leave some space for ACPI, PIRQ and MP tables */
 #if CONFIG_GFXUMA
-			high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+		set_top_of_ram_once(uma_memory_base);
 #else
-			high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
+		set_top_of_ram_once(limitk * 1024);
 #endif
-			high_tables_size = HIGH_MEMORY_SIZE;
-		}
 	}
 
 #if CONFIG_GFXUMA
diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index d670a19..3db3974 100644
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -108,9 +108,7 @@ static void pci_domain_set_resources(device_t dev)
 			tolmk = tomk;
 		}
 
-		/* Leave some space for ACPI, PIRQ and MP tables */
-		high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
+		set_top_of_ram(tolmk * 1024);
 
 		/* Report the memory regions */
 		idx = 10;
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index 038d757..27de1a4 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -290,9 +290,7 @@ static void pci_domain_set_resources(device_t dev)
 		ram_resource(dev, idx++, 0, 640);
 		ram_resource(dev, idx++, 768, tomk - 768);	/* Systop - 0xc0000 -> KB */
 
-		/* Leave some space for ACPI, PIRQ and MP tables */
-		high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
+		set_top_of_ram(tomk * 1024);
 	}
 
 	assign_resources(dev->link_list);
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index bde72a7..4df6879 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -389,9 +389,7 @@ static void pci_domain_set_resources(device_t dev)
 		ram_resource(dev, idx++, 0, 640);
 		ram_resource(dev, idx++, 768, tomk - 768);	// Systop - 0xc0000 -> KB
 
-		/* Leave some space for ACPI, PIRQ and MP tables */
-		high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
+		set_top_of_ram(tomk * 1024);
 	}
 
 	assign_resources(dev->link_list);
diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index d30c9df..0dc7b0b 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -84,9 +84,7 @@ static void pci_domain_set_resources(device_t dev)
 				(remaplimitk + 64*1024) - remapbasek);
 		}
 
-		/* Leave some space for ACPI, PIRQ and MP tables */
-		high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
+		set_top_of_ram(tolmk * 1024);
 	}
 	assign_resources(dev->link_list);
 }
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 6ee371f..4b24b79 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -85,9 +85,7 @@ static void pci_domain_set_resources(device_t dev)
 				(remaplimitk + 64*1024) - remapbasek);
 		}
 
-		/* Leave some space for ACPI, PIRQ and MP tables */
-		high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
+		set_top_of_ram(tolmk * 1024);
 	}
 	assign_resources(dev->link_list);
 }
diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c
index 96fcc35..8b74cec 100644
--- a/src/northbridge/intel/e7520/northbridge.c
+++ b/src/northbridge/intel/e7520/northbridge.c
@@ -102,9 +102,7 @@ static void pci_domain_set_resources(device_t dev)
 				(remaplimitk + 64*1024) - remapbasek);
 		}
 
-		/* Leave some space for ACPI, PIRQ and MP tables */
-		high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
+		set_top_of_ram(tolmk * 1024);
 	}
 	assign_resources(dev->link_list);
 }
diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c
index 83757bd..402dbda 100644
--- a/src/northbridge/intel/e7525/northbridge.c
+++ b/src/northbridge/intel/e7525/northbridge.c
@@ -101,9 +101,7 @@ static void pci_domain_set_resources(device_t dev)
 				(remaplimitk + 64*1024) - remapbasek);
 		}
 
-		/* Leave some space for ACPI, PIRQ and MP tables */
-		high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
+		set_top_of_ram(tolmk * 1024);
 	}
 	assign_resources(dev->link_list);
 }
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 3a4439c..d55a03a 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -166,9 +166,7 @@ static void mch_domain_read_resources(device_t dev)
 			pcie_config_size >> 10, IORESOURCE_RESERVE);
 	}
 
-	/* Leave some space for ACPI, PIRQ and MP tables */
-	high_tables_base = (tomk << 10) - HIGH_MEMORY_SIZE;
-	high_tables_size = HIGH_MEMORY_SIZE;
+	set_top_of_ram(tomk << 10);
 }
 
 static void mch_domain_set_resources(device_t dev)
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index bcaded6..b3349ed 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -126,9 +126,7 @@ static void pci_domain_set_resources(device_t dev)
 				(remaplimitk + 64*1024) - remapbasek);
 		}
 
-		/* Leave some space for ACPI, PIRQ and MP tables */
-		high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
+		set_top_of_ram(tolmk * 1024);
 	}
 	assign_resources(dev->link_list);
 }
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index 2ab62a9..c1aec92 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -67,9 +67,7 @@ static void i440bx_domain_set_resources(device_t dev)
 		ram_resource(dev, idx++, 0, 640);
 		ram_resource(dev, idx++, 768, tolmk - 768);
 
-		/* Leave some space for ACPI, PIRQ and MP tables */
-		high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
+		set_top_of_ram(tomk * 1024);
 	}
 	assign_resources(dev->link_list);
 }
diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c
index fe5f09e..b41a975 100644
--- a/src/northbridge/intel/i440lx/northbridge.c
+++ b/src/northbridge/intel/i440lx/northbridge.c
@@ -93,9 +93,7 @@ static void i440lx_domain_set_resources(device_t dev)
 		ram_resource(dev, idx++, 0, 640);
 		ram_resource(dev, idx++, 768, tolmk - 768);
 
-		/* Leave some space for ACPI, PIRQ and MP tables */
-		high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
+		set_top_of_ram(tomk * 1024);
 	}
 	assign_resources(dev->link_list);
 }
diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c
index 113dc56..3e186fa 100644
--- a/src/northbridge/intel/i5000/northbridge.c
+++ b/src/northbridge/intel/i5000/northbridge.c
@@ -111,10 +111,7 @@ static void mc_read_resources(device_t dev)
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 
-	/* Leave some space for ACPI, PIRQ and MP tables */
-	high_tables_base = tolm - HIGH_MEMORY_SIZE;
-	high_tables_size = HIGH_MEMORY_SIZE;
-	printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size);
+	set_top_of_ram(tolm);
 }
 
 static struct pci_operations intel_pci_ops = {
diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c
index 1d6b66d..3fb3e11 100644
--- a/src/northbridge/intel/i82810/northbridge.c
+++ b/src/northbridge/intel/i82810/northbridge.c
@@ -121,9 +121,7 @@ static void pci_domain_set_resources(device_t dev)
 	ram_resource(dev, idx++, 768, tomk - 768);
 	uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10);
 
-	/* Leave some space for ACPI, PIRQ and MP tables */
-	high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE;
-	high_tables_size = HIGH_MEMORY_SIZE;
+	set_top_of_ram(tomk_stolen * 1024);
 
 	assign_resources(dev->link_list);
 }
diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c
index 881551c..73c28dd 100644
--- a/src/northbridge/intel/i82830/northbridge.c
+++ b/src/northbridge/intel/i82830/northbridge.c
@@ -90,9 +90,7 @@ static void pci_domain_set_resources(device_t dev)
 
 	assign_resources(dev->link_list);
 
-	/* Leave some space for ACPI, PIRQ and MP tables */
-	high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE;
-	high_tables_size = HIGH_MEMORY_SIZE;
+	set_top_of_ram(tomk_stolen * 1024);
 }
 
 static struct device_operations pci_domain_ops = {
diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c
index 75837a1..4c1cd93 100644
--- a/src/northbridge/intel/i855/northbridge.c
+++ b/src/northbridge/intel/i855/northbridge.c
@@ -105,9 +105,7 @@ static void pci_domain_set_resources(device_t dev)
 		/* ram_resource(dev, idx++, 1024, tolmk - 1024); */
 		ram_resource(dev, idx++, 768, tolmk - 768);
 
-		/* Leave some space for ACPI, PIRQ and MP tables */
-		high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
+		set_top_of_ram(tomk * 1024);
 	}
 	assign_resources(dev->link_list);
 }
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 9d97f0c..fc84647 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -170,9 +170,7 @@ static void pci_domain_set_resources(device_t dev)
 
 	assign_resources(dev->link_list);
 
-	/* Leave some space for ACPI, PIRQ and MP tables */
-	high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE;
-	high_tables_size = HIGH_MEMORY_SIZE;
+	set_top_of_ram(tomk_stolen * 1024);
 }
 
 	/* TODO We could determine how many PCIe busses we need in
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index b1a0684..b50f1d8 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -28,11 +28,6 @@
 #include "i945.h"
 #include <cbmem.h>
 
-struct cbmem_entry *get_cbmem_toc(void)
-{
-	return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
-}
-
 /* Debugging macros. */
 #if CONFIG_DEBUG_RAM_SETUP
 #define PRINTK_DEBUG(x...)	printk(BIOS_DEBUG, x)
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 0a413b4..4097b6c 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -259,9 +259,7 @@ static void pci_domain_set_resources(device_t dev)
 
 	assign_resources(dev->link_list);
 
-	/* Leave some space for ACPI, PIRQ and MP tables */
-	high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
-	high_tables_size = HIGH_MEMORY_SIZE;
+	set_top_of_ram(tomk * 1024);
 }
 
 	/* TODO We could determine how many PCIe busses we need in
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 78eedb8..e1fb7f4 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -305,11 +305,6 @@ void sdram_initialize(struct pei_data *pei_data)
 		save_mrc_data(pei_data);
 }
 
-struct cbmem_entry *get_cbmem_toc(void)
-{
-	return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
-}
-
 unsigned long get_top_of_ram(void)
 {
 	/* Base of TSEG is top of usable DRAM */
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index 06d34d8..7cf1db3 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -182,11 +182,7 @@ static void pci_domain_set_resources(device_t dev)
 
 	assign_resources(dev->link_list);
 
-	/* Leave some space for ACPI, PIRQ and MP tables. */
-	high_tables_base = tomk * 1024 - HIGH_MEMORY_SIZE;
-	high_tables_base -= uma_memory_size;
-	high_tables_base -= tseg_memory_base;
-	high_tables_size = HIGH_MEMORY_SIZE;
+	set_top_of_ram(tomk * 1024 - uma_memory_size - tseg_memory_base);
 }
 
 /*
diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c
index e97f10a..2c830ec 100644
--- a/src/northbridge/rdc/r8610/northbridge.c
+++ b/src/northbridge/rdc/r8610/northbridge.c
@@ -64,9 +64,7 @@ static void cpu_pci_domain_set_resources(device_t dev)
 	ram_resource(dev, idx++, 0, 640);
 	ram_resource(dev, idx++, 768, tolmk - 768);
 
-	/* Leave some space for ACPI, PIRQ and MP tables */
-	high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
-	high_tables_size = HIGH_MEMORY_SIZE;
+	set_top_of_ram(tomk * 1024);
 
 	assign_resources(dev->link_list);
 }
diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c
index 0108170..e78d836 100644
--- a/src/northbridge/via/cn400/northbridge.c
+++ b/src/northbridge/via/cn400/northbridge.c
@@ -204,10 +204,7 @@ static void cn400_domain_set_resources(device_t dev)
 		}
 
 		/* Locate the High Tables at the Top of Low Memory below the Video RAM */
-		high_tables_base = ((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
-		printk(BIOS_SPEW, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
-						tomk*1024, high_tables_base, high_tables_size);
+		set_top_of_ram((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024);
 
 		/* Report the memory regions. */
 		idx = 10;
diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c
index 73bf676..c5305d8 100644
--- a/src/northbridge/via/cn700/northbridge.c
+++ b/src/northbridge/via/cn700/northbridge.c
@@ -134,10 +134,7 @@ static void pci_domain_set_resources(device_t dev)
 			tolmk = tomk;
 		}
 
-		high_tables_base = ((tolmk - CONFIG_VIDEO_MB * 1024) * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
-		printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
-						tomk*1024, high_tables_base, high_tables_size);
+		set_top_of_ram((tolmk - CONFIG_VIDEO_MB * 1024) * 1024);
 
 		/* Report the memory regions. */
 		idx = 10;
diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c
index f28a0ed..0d57772 100644
--- a/src/northbridge/via/cx700/northbridge.c
+++ b/src/northbridge/via/cx700/northbridge.c
@@ -68,10 +68,7 @@ static void pci_domain_set_resources(device_t dev)
 		tolmk -= 1024;	// TOP 1M SM Memory
 	}
 
-	high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
-	high_tables_size = HIGH_MEMORY_SIZE;
-	printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
-						tomk*1024, high_tables_base, high_tables_size);
+	set_top_of_ram(tolmk * 1024);
 
 	/* Report the memory regions */
 	idx = 10;
diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index 45a0ac5..aa775f7 100644
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -84,10 +84,7 @@ static void pci_domain_set_resources(device_t dev)
 			tolmk = tomk;
 		}
 
-		high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
-		printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
-				tomk*1024, high_tables_base, high_tables_size);
+		set_top_of_ram(tolmk * 1024);
 
 		/* Report the memory regions */
 		idx = 10;
diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
index f93a886..dd0271a 100644
--- a/src/northbridge/via/vt8623/northbridge.c
+++ b/src/northbridge/via/vt8623/northbridge.c
@@ -143,10 +143,7 @@ static void pci_domain_set_resources(device_t dev)
 			tolmk = tomk;
 		}
 
-		high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
-		high_tables_size = HIGH_MEMORY_SIZE;
-		printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
-						tomk*1024, high_tables_base, high_tables_size);
+		set_top_of_ram(tolmk * 1024);
 
 		/* Report the memory regions */
 		idx = 10;
diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c
index 2439c8d..2896680 100644
--- a/src/northbridge/via/vx900/early_vx900.c
+++ b/src/northbridge/via/vx900/early_vx900.c
@@ -27,11 +27,6 @@ unsigned long get_top_of_ram(void)
 	return (((unsigned long)reg_tom) << 24) - (256 << 20);
 }
 
-struct cbmem_entry *get_cbmem_toc(void)
-{
-	return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
-}
-
 /**
  * \brief Enable accessing of PCI configuration space for all devices.
  *
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index c3c3920..35e2261 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -266,11 +266,7 @@ static void vx900_set_resources(device_t dev)
 	u64 tor = vx900_remap_above_4g(mcu, pci_tolm);
 	ram_resource(dev, idx++, RAM_4GB >> 10, (tor - RAM_4GB) >> 10);
 
-	/* Leave some space for ACPI, PIRQ and MP tables */
-	high_tables_base = (tolmk << 10) - HIGH_MEMORY_SIZE;
-	high_tables_size = HIGH_MEMORY_SIZE;
-	printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n",
-	       high_tables_base, high_tables_size);
+	set_top_of_ram(tolmk << 10);
 
 	print_debug("======================================================\n");
 	assign_resources(dev->link_list);



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